From: DJ Delorie Date: Sat, 22 Oct 2005 00:03:13 +0000 (+0000) Subject: [cpu] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1a280bb84485d80f95e2efc1d02e962e0529652;p=binutils-gdb.git [cpu] * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, indexld, indexls): .w variants have `1' bit. (rot32.b): QI, not SI. (rot32.w): HI, not SI. (xchg16): HI for .w variant. [opcodes] * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. --- diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 0d8f21d9136..6ea2b0e4532 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,12 @@ +2005-10-21 DJ Delorie + + * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. + (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, + indexld, indexls): .w variants have `1' bit. + (rot32.b): QI, not SI. + (rot32.w): HI, not SI. + (xchg16): HI for .w variant. + 2005-10-19 Nick Clifton * m32r.opc (parse_slo16): Fix bad application of previous patch. diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index 095e7cd12ae..93d2bfe598b 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -6702,59 +6702,91 @@ ;------------------------------------------------------------- ; lde dsp24,dst -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 ;------------------------------------------------------------- -(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym lde wstr - dstgroup -u20) + (.str "lde" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) -(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem) + (dni (.sym lde wstr - dstgroup -u20a0) + (.str "lde" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym lde wstr - dstgroup -a1a0) + (.str "lde" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) + +(define-pmacro (lde-dst mode wstr wbit) (begin - (lde-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (lde-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (lde-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) + (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) ;------------------------------------------------------------- -; ste src,dsp24 -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 +; ste dst,dsp24 -- for m16c ;------------------------------------------------------------- -(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym ste wstr - dstgroup -u20) + (.str "ste" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym ste wstr - dstgroup -u20a0) + (.str "ste" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) -(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem) + (dni (.sym ste wstr - dstgroup -a1a0) + (.str "ste" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) + +(define-pmacro (ste-dst mode wstr wbit) (begin - (ste-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (ste-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (ste-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) + (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) @@ -7905,31 +7937,31 @@ ; indexb src (index byte) (unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) -(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) +(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem) ; indexbd src (index byte dest) (unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) -(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) +(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem) ; indexbs src (index byte src) (unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) -(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) +(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem) ; indexl src (index long) (unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) -(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) +(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem) ; indexld src (index long dest) (unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) -(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) +(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem) ; indexls src (index long src) (unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) -(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) +(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem) ; indexw src (index word) (unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) -(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) +(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem) ; indexwd src (index word dest) (unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) -(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) +(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem) ; indexws (index word src) (unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) -(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) +(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem) ;------------------------------------------------------------- ; jcc - jump on condition @@ -8450,21 +8482,11 @@ ; ste - store to extra far data area (m16) ;------------------------------------------------------------- -; A special variant of mem16 for lde and ste -(define-pmacro (extra-mem16 mode address) - (mem mode (and #xfffff address))) +(lde-dst QI .b 0) +(lde-dst HI .w 1) -(define-pmacro (lde-sem mode src1 dst) - (set mode src1 (extra-mem16 mode dst)) -) -(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) -(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) - -(define-pmacro (ste-sem mode src1 dst) - (set (extra-mem16 mode dst) src1) -) -(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) -(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) +(ste-dst QI .b 0) +(ste-dst HI .w 1) ;------------------------------------------------------------- ; ldipl - load interrupt permission level @@ -9481,9 +9503,9 @@ ; rot.BW src,dst (dni rot16.b-dst "rot r1h,dest" ((machine 16)) - ("rot.b r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI) - (rot-2-sem QI dst16-16-HI) + ("rot.b r1h,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) + (rot-2-sem QI dst16-16-QI) ()) (dni rot16.w-dst "rot r1h,dest" ((machine 16)) ("rot.w r1h,${dst16-16-HI}") @@ -9492,14 +9514,14 @@ ()) (dni rot32.b-dst "rot r1h,dest" ((machine 32)) - ("rot.b r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem QI dst32-16-Unprefixed-SI) + ("rot.b r1h,${dst32-16-Unprefixed-QI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem QI dst32-16-Unprefixed-QI) ()) (dni rot32.w-dst "rot r1h,dest" ((machine 32)) - ("rot.w r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem HI dst32-16-Unprefixed-SI) + ("rot.w r1h,${dst32-16-Unprefixed-HI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem HI dst32-16-Unprefixed-HI) ()) ;------------------------------------------------------------- @@ -10215,7 +10237,7 @@ (xchg16-defn QI b 0 1 r0h) (xchg16-defn QI b 0 2 r1l) (xchg16-defn QI b 0 3 r1h) -(xchg16-defn QI w 1 0 r0) +(xchg16-defn HI w 1 0 r0) (xchg16-defn HI w 1 1 r1) (xchg16-defn HI w 1 2 r2) (xchg16-defn HI w 1 3 r3) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4a55a286e21..d3f729d2446 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2005-10-21 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + 2005-10-21 Nick Clifton * bfin-dis.c: Tidy up code, removing redundant constructs. diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index 1bfa926efdb..fdd15141f76 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -879,6 +879,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_A1 : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk); break; + case M32C_OPERAND_A1A0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & junk); + break; case M32C_OPERAND_AN16_PUSH_S : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1); break; diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index a86c086a773..01c521569b0 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -1422,6 +1422,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<f_4_1, 0); break; diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index f5c2dc32946..bbf9a870352 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -562,6 +562,8 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, break; case M32C_OPERAND_A1 : break; + case M32C_OPERAND_A1A0 : + break; case M32C_OPERAND_AN16_PUSH_S : errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); break; @@ -1709,6 +1711,8 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, break; case M32C_OPERAND_A1 : break; + case M32C_OPERAND_A1A0 : + break; case M32C_OPERAND_AN16_PUSH_S : length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); break; @@ -2818,6 +2822,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_A1 : value = 0; break; + case M32C_OPERAND_A1A0 : + value = 0; + break; case M32C_OPERAND_AN16_PUSH_S : value = fields->f_4_1; break; @@ -3399,6 +3406,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_A1 : value = 0; break; + case M32C_OPERAND_A1A0 : + value = 0; + break; case M32C_OPERAND_AN16_PUSH_S : value = fields->f_4_1; break; @@ -3985,6 +3995,8 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, break; case M32C_OPERAND_A1 : break; + case M32C_OPERAND_A1A0 : + break; case M32C_OPERAND_AN16_PUSH_S : fields->f_4_1 = value; break; @@ -4544,6 +4556,8 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, break; case M32C_OPERAND_A1 : break; + case M32C_OPERAND_A1A0 : + break; case M32C_OPERAND_AN16_PUSH_S : fields->f_4_1 = value; break; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index eeb7321f7d1..2ca538ea237 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -2825,39 +2825,39 @@ static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_direct_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = { 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; -static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } }; @@ -6729,75 +6729,75 @@ static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_ 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { - 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { - 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { - 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { - 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { - 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { - 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = { 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { - 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { - 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { - 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { - 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { - 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { - 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = { 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } }; @@ -13458,275 +13458,275 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } }, & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 } }, -/* xchg.w r0,$Dst16RnQI */ +/* xchg.w r0,$Dst16RnHI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '0', ',', OP (DST16RNQI), 0 } }, - & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7b00 } + { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 } }, -/* xchg.w r0,$Dst16AnQI */ +/* xchg.w r0,$Dst16AnHI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '0', ',', OP (DST16ANQI), 0 } }, - & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7b04 } + { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 } }, /* xchg.w r0,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7b06 } + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 } }, /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7b0800 } + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 } }, /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7b0c0000 } + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 } }, /* xchg.w r0,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7b0a00 } + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 } }, /* xchg.w r0,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7b0e0000 } + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 } }, /* xchg.w r0,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7b0b00 } + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 } }, /* xchg.w r0,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7b0f0000 } + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 } }, /* xchg.b r1h,$Dst16RnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, - & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a30 } + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 } }, /* xchg.b r1h,$Dst16AnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, - & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a34 } + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 } }, /* xchg.b r1h,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a36 } + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 } }, /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a3800 } + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 } }, /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a3c0000 } + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 } }, /* xchg.b r1h,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a3a00 } + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 } }, /* xchg.b r1h,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a3e0000 } + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 } }, /* xchg.b r1h,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a3b00 } + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 } }, /* xchg.b r1h,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a3f0000 } + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 } }, /* xchg.b r1l,$Dst16RnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } }, - & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a20 } + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 } }, /* xchg.b r1l,$Dst16AnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } }, - & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a24 } + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 } }, /* xchg.b r1l,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a26 } + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 } }, /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a2800 } + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 } }, /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a2c0000 } + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 } }, /* xchg.b r1l,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a2a00 } + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 } }, /* xchg.b r1l,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a2e0000 } + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 } }, /* xchg.b r1l,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a2b00 } + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 } }, /* xchg.b r1l,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a2f0000 } + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 } }, /* xchg.b r0h,$Dst16RnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } }, - & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a10 } + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 } }, /* xchg.b r0h,$Dst16AnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } }, - & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a14 } + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 } }, /* xchg.b r0h,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a16 } + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 } }, /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a1800 } + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 } }, /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a1c0000 } + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 } }, /* xchg.b r0h,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a1a00 } + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 } }, /* xchg.b r0h,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a1e0000 } + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 } }, /* xchg.b r0h,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a1b00 } + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 } }, /* xchg.b r0h,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a1f0000 } + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 } }, /* xchg.b r0l,$Dst16RnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, - & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a00 } + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 } }, /* xchg.b r0l,$Dst16AnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, - & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a04 } + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 } }, /* xchg.b r0l,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a06 } + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 } }, /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a0800 } + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 } }, /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a0c0000 } + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 } }, /* xchg.b r0l,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a0a00 } + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 } }, /* xchg.b r0l,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a0e0000 } + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 } }, /* xchg.b r0l,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a0b00 } + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 } }, /* xchg.b r0l,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, - & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a0f0000 } + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 } }, /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { @@ -22872,149 +22872,149 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 } }, -/* rot.w r1h,$Dst32RnUnprefixedSI */ +/* rot.w r1h,$Dst32RnUnprefixedHI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, - & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa93f } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f } }, -/* rot.w r1h,$Dst32AnUnprefixedSI */ +/* rot.w r1h,$Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, - & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa1bf } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf } }, /* rot.w r1h,[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa13f } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f } }, /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa33f00 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 } }, /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa53f0000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 } }, /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa73f0000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 } }, /* rot.w r1h,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa3bf00 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 } }, /* rot.w r1h,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa5bf0000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 } }, /* rot.w r1h,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa3ff00 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 } }, /* rot.w r1h,${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa5ff0000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 } }, /* rot.w r1h,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa7ff0000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 } }, /* rot.w r1h,${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa7bf0000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 } }, -/* rot.b r1h,$Dst32RnUnprefixedSI */ +/* rot.b r1h,$Dst32RnUnprefixedQI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, - & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa83f } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f } }, -/* rot.b r1h,$Dst32AnUnprefixedSI */ +/* rot.b r1h,$Dst32AnUnprefixedQI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, - & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0bf } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf } }, /* rot.b r1h,[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa03f } + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f } }, /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa23f00 } + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 } }, /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa43f0000 } + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 } }, /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa63f0000 } + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2bf00 } + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4bf0000 } + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2ff00 } + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 } }, /* rot.b r1h,${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4ff0000 } + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 } }, /* rot.b r1h,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6ff0000 } + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 } }, /* rot.b r1h,${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6bf0000 } + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 } }, /* rot.w r1h,$Dst16RnHI */ { @@ -23070,59 +23070,59 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 } }, -/* rot.b r1h,$Dst16RnHI */ +/* rot.b r1h,$Dst16RnQI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, - & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7460 } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 } }, -/* rot.b r1h,$Dst16AnHI */ +/* rot.b r1h,$Dst16AnQI */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, - & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7464 } + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 } }, /* rot.b r1h,[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7466 } + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 } }, /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x746800 } + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 } }, /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x746c0000 } + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x746a00 } + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x746e0000 } + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x746b00 } + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 } }, /* rot.b r1h,${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, - & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x746f0000 } + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 } }, /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { @@ -44424,221 +44424,653 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 } }, -/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ +/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75080000 } + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 } }, -/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */ +/* ste.w ${Dsp-16-u16}[sb],[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x750a0000 } + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 } }, -/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */ +/* ste.w ${Dsp-16-u16},[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x750b0000 } + { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 } + }, +/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 } + }, +/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 } + }, +/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 } }, /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x750c0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 } }, /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x750e0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 } }, /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x750f0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 } + }, +/* ste.w ${Dsp-16-u8}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 } + }, +/* ste.w ${Dsp-16-s8}[fb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 } + }, +/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 } + }, +/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 } + }, +/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 } + }, +/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 } + }, +/* ste.w $Dst16RnHI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 } + }, +/* ste.w $Dst16AnHI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 } + }, +/* ste.w [$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 } + }, +/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 } + }, +/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 } + }, +/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 } }, /* ste.w $Dst16RnHI,${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75000000 } + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 } }, /* ste.w $Dst16AnHI,${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75040000 } + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 } }, /* ste.w [$Dst16An],${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75060000 } + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 } }, -/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ +/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74080000 } + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 } }, -/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */ +/* ste.b ${Dsp-16-u16}[sb],[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x740a0000 } + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 } }, -/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */ +/* ste.b ${Dsp-16-u16},[a1a0] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x740b0000 } + { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 } + }, +/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 } + }, +/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 } + }, +/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 } }, /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x740c0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 } }, /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x740e0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 } }, /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x740f0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 } + }, +/* ste.b ${Dsp-16-u8}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 } + }, +/* ste.b ${Dsp-16-s8}[fb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 } + }, +/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 } + }, +/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 } + }, +/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 } + }, +/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 } + }, +/* ste.b $Dst16RnQI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 } + }, +/* ste.b $Dst16AnQI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 } + }, +/* ste.b [$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 } + }, +/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 } + }, +/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 } + }, +/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 } }, /* ste.b $Dst16RnQI,${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74000000 } + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 } }, /* ste.b $Dst16AnQI,${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74040000 } + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 } }, /* ste.b [$Dst16An],${Dsp-16-u20} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74060000 } + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 } }, -/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ +/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75880000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 } }, -/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */ +/* lde.w [a1a0],${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x758a0000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 } }, -/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */ +/* lde.w [a1a0],${Dsp-16-u16} */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x758b0000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x758c0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x758e0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, - & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x758f0000 } + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 } + }, +/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 } + }, +/* lde.w [a1a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 } + }, +/* lde.w [a1a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 } + }, +/* lde.w [a1a0],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 } + }, +/* lde.w [a1a0],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 } + }, +/* lde.w [a1a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 } + }, +/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 } + }, +/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 } + }, +/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 } }, /* lde.w ${Dsp-16-u20},$Dst16RnHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75800000 } + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 } }, /* lde.w ${Dsp-16-u20},$Dst16AnHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75840000 } + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 } }, /* lde.w ${Dsp-16-u20},[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75860000 } + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 } }, -/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ +/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74880000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 } }, -/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */ +/* lde.b [a1a0],${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x748a0000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 } }, -/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */ +/* lde.b [a1a0],${Dsp-16-u16} */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x748b0000 } + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x748c0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x748e0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, - & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x748f0000 } + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 } + }, +/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 } + }, +/* lde.b [a1a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 } + }, +/* lde.b [a1a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 } + }, +/* lde.b [a1a0],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 } + }, +/* lde.b [a1a0],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 } + }, +/* lde.b [a1a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 } + }, +/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 } + }, +/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 } + }, +/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 } }, /* lde.b ${Dsp-16-u20},$Dst16RnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74800000 } + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 } }, /* lde.b ${Dsp-16-u20},$Dst16AnQI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74840000 } + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 } }, /* lde.b ${Dsp-16-u20},[$Dst16An] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, - & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74860000 } + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 } }, /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */ { @@ -45742,73 +46174,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc933 } }, /* indexws.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1b3 } }, /* indexws.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc133 } }, /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33300 } }, /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5330000 } }, /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7330000 } }, /* indexws.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3b300 } }, /* indexws.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5b30000 } }, /* indexws.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3f300 } }, /* indexws.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5f30000 } }, /* indexws.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7f30000 } }, /* indexws.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7b30000 } }, /* indexws.b $Dst32RnUnprefixedQI */ { @@ -45886,73 +46318,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa933 } }, /* indexwd.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1b3 } }, /* indexwd.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa133 } }, /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33300 } }, /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5330000 } }, /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7330000 } }, /* indexwd.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3b300 } }, /* indexwd.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5b30000 } }, /* indexwd.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3f300 } }, /* indexwd.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5f30000 } }, /* indexwd.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7f30000 } }, /* indexwd.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7b30000 } }, /* indexwd.b $Dst32RnUnprefixedQI */ { @@ -46030,73 +46462,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8933 } }, /* indexw.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x81b3 } }, /* indexw.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8133 } }, /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x833300 } }, /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85330000 } }, /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87330000 } }, /* indexw.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83b300 } }, /* indexw.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85b30000 } }, /* indexw.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83f300 } }, /* indexw.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85f30000 } }, /* indexw.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87f30000 } }, /* indexw.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87b30000 } }, /* indexw.b $Dst32RnUnprefixedQI */ { @@ -46174,73 +46606,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9913 } }, /* indexls.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9193 } }, /* indexls.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9113 } }, /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931300 } }, /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95130000 } }, /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97130000 } }, /* indexls.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939300 } }, /* indexls.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95930000 } }, /* indexls.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93d300 } }, /* indexls.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95d30000 } }, /* indexls.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97d30000 } }, /* indexls.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97930000 } }, /* indexls.b $Dst32RnUnprefixedQI */ { @@ -46318,73 +46750,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb933 } }, /* indexld.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1b3 } }, /* indexld.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb133 } }, /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33300 } }, /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb5330000 } }, /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb7330000 } }, /* indexld.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3b300 } }, /* indexld.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5b30000 } }, /* indexld.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3f300 } }, /* indexld.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5f30000 } }, /* indexld.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7f30000 } }, /* indexld.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7b30000 } }, /* indexld.b $Dst32RnUnprefixedQI */ { @@ -46462,73 +46894,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9933 } }, /* indexl.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x91b3 } }, /* indexl.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9133 } }, /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x933300 } }, /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95330000 } }, /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97330000 } }, /* indexl.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93b300 } }, /* indexl.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95b30000 } }, /* indexl.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93f300 } }, /* indexl.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95f30000 } }, /* indexl.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97f30000 } }, /* indexl.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97b30000 } }, /* indexl.b $Dst32RnUnprefixedQI */ { @@ -46606,73 +47038,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc913 } }, /* indexbs.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc193 } }, /* indexbs.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc113 } }, /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31300 } }, /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5130000 } }, /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7130000 } }, /* indexbs.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39300 } }, /* indexbs.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5930000 } }, /* indexbs.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3d300 } }, /* indexbs.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5d30000 } }, /* indexbs.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7d30000 } }, /* indexbs.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7930000 } }, /* indexbs.b $Dst32RnUnprefixedQI */ { @@ -46750,73 +47182,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa913 } }, /* indexbd.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa193 } }, /* indexbd.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa113 } }, /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31300 } }, /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5130000 } }, /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7130000 } }, /* indexbd.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39300 } }, /* indexbd.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5930000 } }, /* indexbd.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3d300 } }, /* indexbd.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5d30000 } }, /* indexbd.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7d30000 } }, /* indexbd.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7930000 } }, /* indexbd.b $Dst32RnUnprefixedQI */ { @@ -46894,73 +47326,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, - & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 } + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8913 } }, /* indexb.w $Dst32AnUnprefixedHI */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, - & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 } + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8193 } }, /* indexb.w [$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 } + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8113 } }, /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 } + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831300 } }, /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 } + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85130000 } }, /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 } + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87130000 } }, /* indexb.w ${Dsp-16-u8}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 } + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839300 } }, /* indexb.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 } + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85930000 } }, /* indexb.w ${Dsp-16-s8}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 } + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83d300 } }, /* indexb.w ${Dsp-16-s16}[fb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 } + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85d30000 } }, /* indexb.w ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 } + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87d30000 } }, /* indexb.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 } + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87930000 } }, /* indexb.b $Dst32RnUnprefixedQI */ { diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h index 4e49ff454d6..bc7c000a9bc 100644 --- a/opcodes/m32c-opc.h +++ b/opcodes/m32c-opc.h @@ -286,9 +286,9 @@ typedef enum cgen_insn_type { , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI - , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI - , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI - , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI + , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI @@ -678,17 +678,17 @@ typedef enum cgen_insn_type { , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI - , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI - , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI - , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI - , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI + , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI @@ -1576,16 +1576,34 @@ typedef enum cgen_insn_type { , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI , M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI - , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI - , M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI - , M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI - , M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI - , M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI - , M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI - , M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI - , M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI - , M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI - , M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI + , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI + , M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI + , M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI + , M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI + , M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI + , M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI