From: Jakub Jelinek <jakub@redhat.com>
Date: Tue, 20 Jun 2017 07:04:27 +0000 (+0200)
Subject: re PR target/81121 (ICE: in extract_insn, at recog.c:2311)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1aa2599dd85d590f39dbe565cc213c8dab65cae;p=gcc.git

re PR target/81121 (ICE: in extract_insn, at recog.c:2311)

	PR target/81121
	* config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df}
	splitter): Require TARGET_SSE2 in the condition.

	* gcc.target/i386/pr81121.c: New test.

From-SVN: r249396
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5af9611b837..06e0cec4d14 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/81121
+	* config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df}
+	splitter): Require TARGET_SSE2 in the condition.
+
 2017-06-20  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR target/79799
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index adc13a9afbc..40a20d0ec6e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5290,7 +5290,8 @@
 (define_split
   [(set (match_operand:MODEF 0 "sse_reg_operand")
 	(float:MODEF (match_operand:SI 1 "nonimmediate_operand")))]
-  "TARGET_USE_VECTOR_CONVERTS
+  "TARGET_SSE2
+   && TARGET_USE_VECTOR_CONVERTS
    && optimize_function_for_speed_p (cfun)
    && reload_completed
    && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0809b2cd70a..330a1085416 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/81121
+	* gcc.target/i386/pr81121.c: New test.
+
 2017-06-20  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR target/79799
diff --git a/gcc/testsuite/gcc.target/i386/pr81121.c b/gcc/testsuite/gcc.target/i386/pr81121.c
new file mode 100644
index 00000000000..aca74e95b46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr81121.c
@@ -0,0 +1,10 @@
+/* PR target/81121 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=amdfam10 -mno-sse2" } */
+
+void
+foo (short *x, short *y)
+{
+  float a = 0;
+  y[0] = x[0] * a;
+}