From: IkiWiki <ikiwiki.info>
Date: Thu, 29 Sep 2022 22:47:13 +0000 (+0100)
Subject: dummy commit
X-Git-Tag: opf_rfc_ls005_v1~260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1ac6cdb3ac61570b729b6dd8863a6b60c5a7810;p=libreriscv.git

dummy commit
---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 86d46a816..09cdb52dc 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -156,7 +156,7 @@ strongly recommended, to avoid a Read-Modify-Write cycle.
 The only major concern is in the upper SV Extension Levels: the Hazard
 Management for increased number of Scalar Registers to 128 (in current
 versions) but given that IBM POWER9/10 has VSX register numbering 64,
-and modern GPUs have 128, 256 amd even 512 registers this was deemed
+and modern GPUs have 128, 256 and even 512 registers this was deemed
 acceptable. Strategies do exist in hardware for Hazard Management of
 such large numbers of registers, even for Multi-Issue microarchitectures.