From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 17 Feb 2012 10:08:41 +0000 (+0100)
Subject: fhdl/verilog: properly connect instance inouts
X-Git-Tag: 24jan2021_ls180~2099^2~1012
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1ad30faab428905349214643837a1deed861b20;p=litex.git

fhdl/verilog: properly connect instance inouts
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 3b6655e7..e68071ae 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst):
 		r += ns.get_name(x) 
 		if x.parameters: r += " "
 		r += "(\n"
-		ports = list(x.ins.items()) + list(x.outs.items())
+		ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items())
 		if x.clkport:
 			ports.append((x.clkport, clk))
 		if x.rstport: