From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 12:17:33 +0000 (+0100) Subject: clarify interoperability X-Git-Tag: opf_rfc_ls005_v1~501 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1bc5649d55c4c9c260b780fc65ad1f88cbfd01b;p=libreriscv.git clarify interoperability --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index dc7ba5591..33351a0d9 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -78,16 +78,19 @@ to be reserved. Power ISA is long-term stable. A catastrophic mistake has been made in ARM SVE/2 and RISC-V RVV: "Silicon-Partner" Scalability, marketed as a feature, allows the same instructions to mean different things on -different implementations (a different Vector bitwidth). This means -that binary interoperability is not only impossible to achieve but +different implementations (a different Vector bitwidth). +Binary interoperability is thus not only impossible to achieve but Illegal Instruction trap-and-emulate is also out of the question. -Worse than that a **future** vendor implementation may suddenly render -**all existing** hardware non-interoperable. +Worse than that a **future** vendor may suddenly render +**all existing** hardware non-interoperable. It is the worst possible +thing for any specification to permit new vendors to damage earlier +implementations, yet this is what is permitted in SVE and RVV +*by design*. **Simple-V guarantees binary interoperability** by defining fixed register file bitwidths and size for all instructions. This does mean that `RESERVED` space is important to have in SVP64, in order -to provide future expanded register file bitwidths and sizes. [^msr] +to safely provide future expanded register file bitwidths and sizes.[^msr] # Hardware Implementations