From: Clifford Wolf Date: Sun, 5 Apr 2015 16:04:19 +0000 (+0200) Subject: Avoid parameter values with size 0 ($mem cells) X-Git-Tag: yosys-0.6~359 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1c62b79d5d554be86b4b9bd53d72704b045acde;p=yosys.git Avoid parameter values with size 0 ($mem cells) --- diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6de5846f9..2dff53b7b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -918,11 +918,11 @@ namespace { param("\\SIZE"); param("\\OFFSET"); param("\\INIT"); - param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS")); - param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS")); - param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS")); - param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS")); - param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS")); + param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS"))); + param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS"))); + param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS"))); + param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS"))); + param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS"))); port("\\RD_CLK", param("\\RD_PORTS")); port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 96d0ada03..7e088a1b0 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -178,8 +178,8 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 1); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 1); mem->setPort("\\WR_CLK", sig_wr_clk); mem->setPort("\\WR_ADDR", sig_wr_addr); @@ -193,9 +193,9 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 1); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 1); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 1); mem->setPort("\\RD_CLK", sig_rd_clk); mem->setPort("\\RD_ADDR", sig_rd_addr); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 41c4a7b12..bc94e1e25 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -81,6 +81,9 @@ struct MemoryMapWorker std::set static_ports; std::map static_cells_map; + int wr_ports = cell->parameters["\\WR_PORTS"].as_int(); + int rd_ports = cell->parameters["\\RD_PORTS"].as_int(); + int mem_size = cell->parameters["\\SIZE"].as_int(); int mem_width = cell->parameters["\\WIDTH"].as_int(); int mem_offset = cell->parameters["\\OFFSET"].as_int(); @@ -90,7 +93,7 @@ struct MemoryMapWorker init_data.extend_u0(mem_size*mem_width, true); // delete unused memory cell - if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { + if (wr_ports == 0 && rd_ports == 0) { module->remove(cell); return; } @@ -99,6 +102,8 @@ struct MemoryMapWorker RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + clocks_pol.bits.resize(wr_ports); + clocks_en.bits.resize(wr_ports); RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) {