From: Luke Kenneth Casson Leighton Date: Fri, 19 Oct 2018 13:52:15 +0000 (+0100) Subject: redirect obtaining registers through a common function, get_intreg X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1cde0d62561c8ae3929a8b51b8043f68045e818;p=riscv-isa-sim.git redirect obtaining registers through a common function, get_intreg --- diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index c34d291..19df7b7 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -100,13 +100,18 @@ sv_reg_t (sv_proc_t::READ_REG)(uint64_t i) } */ +sv_reg_t sv_proc_t::get_intreg(reg_t reg) +{ + uint8_t elwidth = _insn->reg_elwidth(reg, true); + uint64_t data = _insn->p->get_state()->XPR[reg]; + return sv_reg_t(data, elwidth); +} + #define GET_REG(name) \ sv_reg_t sv_proc_t::get_##name() \ { \ reg_t reg = _insn->name (); \ - uint8_t elwidth = _insn->reg_elwidth(reg, true); \ - uint64_t data = _insn->p->get_state()->XPR[reg]; \ - return sv_reg_t(data, elwidth); \ + return get_intreg(reg); \ } GET_REG(rs1) @@ -129,12 +134,12 @@ freg_t sv_proc_t::get_frs2() sv_reg_t sv_proc_t::get_shamt() { - return sv_reg_t(_insn->i_imm() & 0x3F); + return sv_reg_t(_insn->i_imm() & 0x3F); // XXX TODO: has to be elwidth'd } sv_reg_t sv_proc_t::get_rvc_sp() { - return (_insn->p->get_state()->XPR[X_SP]); + return get_intreg(X_SP); // XXX TODO: work out redirection } sv_reg_t sv_proc_t::uint64_max() diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index 9d09eb7..4e132f3 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -87,6 +87,10 @@ public: this->insn._insn = i; } +private: + sv_reg_t get_intreg(reg_t reg); + +public: sv_reg_t get_rs1(); sv_reg_t get_rs2(); sv_reg_t get_rs3();