From: William D. Jones <thor0505@comcast.net>
Date: Mon, 1 Feb 2021 00:05:15 +0000 (-0500)
Subject: machxo2: Fix reversed interpretation of REG_SD config bits.
X-Git-Tag: working-ls180~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1ea1430b6ba478267d30253a79936fcb9e5faef;p=yosys.git

machxo2: Fix reversed interpretation of REG_SD config bits.
---

diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 5f985d477..e046d0c87 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -146,8 +146,8 @@ module FACADE_SLICE #(
 
 	/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
 	outputs (in other words, feeds back into FACADE_SLICE). */
-	wire di0 = (REG0_SD == "1") ? M0 : DI0;
-	wire di1 = (REG1_SD == "1") ? M1 : DI1;
+	wire di0 = (REG0_SD == "1") ? DI0 : M0;
+	wire di1 = (REG1_SD == "1") ? DI1 : M1;
 
 	FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
 		.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),