From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Dec 2023 10:11:28 +0000 (+0000)
Subject: take every opportunity *not* to go onto a separate line with commas
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1edfec3223092d2dc5fd652af678caaa2b2429e;p=openpower-isa.git

take every opportunity *not* to go onto a separate line with commas

bad:
-        log("is priv", instr_is_privileged, hex(self.msr.value),
-            self.msr[MSRb.PR])

good:
-        if instr_is_privileged and self.msr[MSRb.PR] == 1:
+        PR = self.msr[MSRb.PR]
+        log("is priv", instr_is_privileged, hex(self.msr.value), PR)
+        if instr_is_privileged and PR == 1:
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 2385ecf0..46876cf9 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2133,10 +2133,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                       MicrOp.OP_MTSPR.value] and spr_msb:
             instr_is_privileged = True
 
-        log("is priv", instr_is_privileged, hex(self.msr.value),
-            self.msr[MSRb.PR])
         # check MSR priv bit and whether op is privileged: if so, throw trap
-        if instr_is_privileged and self.msr[MSRb.PR] == 1:
+        PR = self.msr[MSRb.PR]
+        log("is priv", instr_is_privileged, hex(self.msr.value), PR)
+        if instr_is_privileged and PR == 1:
             self.call_trap(0x700, PIb.PRIV)
             return