From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Sep 2022 13:39:27 +0000 (+0100)
Subject: set srcstep/dststep to zero in StepLoop (ISACaller) at loopend
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1f4452076ea05cfad2c93b2536734fa4a767926;p=openpower-isa.git

set srcstep/dststep to zero in StepLoop (ISACaller) at loopend
see if a different style of looping can be used
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 942987d9..1bc5bed4 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -732,6 +732,7 @@ class StepLoop:
                     end_src = srcstep == vl-1
                     if end_src:  # end-point
                         self.loopend = True
+                        srcstep = 0
                         break
                     else:
                         srcstep += 1
@@ -794,6 +795,7 @@ class StepLoop:
                     end_dst = dststep == vl-1
                     if end_dst:  # end-point
                         self.loopend = True
+                        dststep = 0
                         break
                     else:
                         dststep += 1