From: Sebastien Bourdeauducq Date: Thu, 12 Dec 2013 23:02:50 +0000 (+0100) Subject: fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems X-Git-Tag: 24jan2021_ls180~2099^2~388 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a20688f777e360e60a78e90d011538d02ca9887b;p=litex.git fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems --- diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py index 5876b013..b84b5cc9 100644 --- a/migen/fhdl/simplify.py +++ b/migen/fhdl/simplify.py @@ -27,7 +27,7 @@ class FullMemoryWE(ModuleDecorator): newport = _MemoryPort(adr=port.adr, dat_r=port.dat_r[i*global_granularity:(i+1)*global_granularity] if port.dat_r is not None else None, - we=port.we[i*port_granularity//global_granularity] if port.we is not None else None, + we=port.we[i*global_granularity//port_granularity] if port.we is not None else None, dat_w=port.dat_w[i*global_granularity:(i+1)*global_granularity] if port.dat_w is not None else None, async_read=port.async_read,