From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Tue, 6 Jun 2017 00:05:02 +0000 (-0700)
Subject: i965: Move the post-HiZ-clear flush/stall to intel_hiz_exec
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2152775fd57fb33a1100cd6b2ec609cf3a79b6c;p=mesa.git

i965: Move the post-HiZ-clear flush/stall to intel_hiz_exec

This also changes it to be predicated so we only do the flush/stall on
clears and HiZ resolves.  The docs only say it's needed for clears but
empirical evidence says it's also needed for HiZ resolves.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 834f43249a9..568ff6980e8 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1098,6 +1098,24 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
          brw_emit_pipe_control_flush(brw,
                                      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                      PIPE_CONTROL_CS_STALL);
+      } else if (brw->gen >= 8) {
+         /*
+          * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
+          *
+          *    "Depth buffer clear pass using any of the methods (WM_STATE,
+          *    3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+          *    PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+          *    "set" before starting to render.  DepthStall and DepthFlush are
+          *    not needed between consecutive depth clear passes nor is it
+          *    required if the depth clear pass was done with
+          *    'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
+          *
+          *  TODO: Such as the spec says, this could be conditional.
+          */
+         brw_emit_pipe_control_flush(brw,
+                                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                     PIPE_CONTROL_DEPTH_STALL);
+
       }
    }
 }
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 0fafd7c7459..e7c7b9a4bd7 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -524,22 +524,6 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
    OUT_BATCH(0);
    ADVANCE_BATCH();
 
-   /*
-    * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
-    *
-    *  Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
-    *  or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
-    *  DEPTH_STALL bit and Depth FLUSH bits "set" before starting to render.
-    *  DepthStall and DepthFlush are not needed between consecutive depth
-    *  clear passes nor is it required if th e depth clear pass was done with
-    *  "full_surf_clear" bit set in the 3DSTATE_WM_HZ_OP.
-    *
-    *  TODO: Such as the spec says, this could be conditional.
-    */
-   brw_emit_pipe_control_flush(brw, 
-                               PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                               PIPE_CONTROL_DEPTH_STALL);
-
    /* Mark this buffer as needing a TC flush, as we've rendered to it. */
    brw_render_cache_set_add_bo(brw, mt->bo);