From: Luke Kenneth Casson Leighton Date: Tue, 31 Dec 2019 05:54:31 +0000 (+0000) Subject: clarification X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a21ef68f03495ac68e1b73ce54184d3175c77e1b;p=crowdsupply.git clarification --- diff --git a/updates/021_2019dec29_nlnet_grants_approved.mdwn b/updates/021_2019dec29_nlnet_grants_approved.mdwn index e11ea6c..c9620ff 100644 --- a/updates/021_2019dec29_nlnet_grants_approved.mdwn +++ b/updates/021_2019dec29_nlnet_grants_approved.mdwn @@ -169,13 +169,13 @@ with a *userspace* RV64GC dual-ISA front-end. **Userspace** RISC-V POSIX PowerISA POSIX applications, however the **kernel** (supervisor) space will be entirely PowerISA. -The video and 3D acceleration opcodes will be **entirely in the Power ISA**. -We are sick and tired of the RISC-V Foundation's blatant mismanagement. -Therefore, we will comply to the absolute minimal letter with RV64GC for -the benefit of our users, backers, and sponsors. However, RISC-V and the -RISC-V ISA itself -will no longer receive the benefit of the advancements and innovation -that we have received funding and support to develop. +The video and 3D acceleration opcodes will be **entirely in the Power +ISA**. We are sick and tired of the RISC-V Foundation's intransigence +and blatant mismanagement. Therefore, we will comply to the absolute +minimal letter with RV64GC for the benefit of our users, backers, and +sponsors who will be expecting RISC-V Compliance. However, RISC-V and the +RISC-V ISA itself will no longer receive the benefit of the advancements +and innovation that we have received funding and support to develop. So, the assembly-code being written by hand for the video acceleration side, as well as the 3D drivers for Kazan and MESA, will "flip" from RV64GC