From: Gabe Black <gabeblack@google.com>
Date: Fri, 12 Oct 2018 12:03:38 +0000 (-0700)
Subject: arch: Explicitly specify the endianness in the generic mem helpers.
X-Git-Tag: v19.0.0.0~1585
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a22030133d9bed4e4e93f549b7993705421be845;p=gem5.git

arch: Explicitly specify the endianness in the generic mem helpers.

This avoids using the accessors which automatically assume an
endianness, requiring the memory system to know what the guest ISA is.

Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f
Reviewed-on: https://gem5-review.googlesource.com/c/13461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index 6fe1707a0..7fd4f70de 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -66,7 +66,7 @@ template <class MemT>
 void
 getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 {
-    mem = pkt->get<MemT>();
+    mem = pkt->get<MemT>(TheISA::GuestByteOrder);
     if (traceData)
         traceData->setData(mem);
 }
diff --git a/src/arch/generic/mmapped_ipr.cc b/src/arch/generic/mmapped_ipr.cc
index c908eff01..14e2bafbd 100644
--- a/src/arch/generic/mmapped_ipr.cc
+++ b/src/arch/generic/mmapped_ipr.cc
@@ -47,7 +47,7 @@ handlePseudoInst(ThreadContext *xc, Packet *pkt)
     assert((offset >> 16) == 0);
     ret = PseudoInst::pseudoInst(xc, func, subfunc);
     if (pkt->isRead())
-        pkt->set(ret);
+        pkt->set(ret, TheISA::GuestByteOrder);
 }
 
 Cycles