From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Fri, 29 Oct 2021 16:25:35 +0000 (+0200)
Subject: cores.litedram: add SDR DRAM type.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a238c6222980eac08a4e288d6974e0ce67b95849;p=lambdasoc.git

cores.litedram: add SDR DRAM type.
---

diff --git a/lambdasoc/cores/litedram.py b/lambdasoc/cores/litedram.py
index 31a3a35..11c4700 100644
--- a/lambdasoc/cores/litedram.py
+++ b/lambdasoc/cores/litedram.py
@@ -73,13 +73,15 @@ class Config(metaclass=ABCMeta):
             cmd_buffer_depth = 16,
             csr_data_width   = 32):
 
-        if memtype == "DDR2":
+        if memtype == "SDR":
+            rate = "1:1"
+        elif memtype in {"DDR", "LPDDR", "DDR2"}:
             rate = "1:2"
         elif memtype in {"DDR3", "DDR4"}:
             rate = "1:4"
         else:
-            raise ValueError("Unsupported DRAM type, must be one of \"DDR2\", \"DDR3\" or "
-                             "\"DDR4\", not {!r}"
+            raise ValueError("Unsupported DRAM type, must be one of \"SDR\", \"DDR\", \"LPDDR\", "
+                             "\"DDR2\", \"DDR3\" or \"DDR4\", not {!r}"
                              .format(memtype))
 
         if not isinstance(module_name, str):