From: Sebastien Bourdeauducq Date: Tue, 12 Mar 2013 14:47:54 +0000 (+0100) Subject: Use automatic register naming X-Git-Tag: 24jan2021_ls180~3033 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a23df42a7a0e58e09c96084d140f94d25df330c4;p=litex.git Use automatic register naming --- diff --git a/milkymist/asmiprobe/__init__.py b/milkymist/asmiprobe/__init__.py index 69844850..f210c13b 100644 --- a/milkymist/asmiprobe/__init__.py +++ b/milkymist/asmiprobe/__init__.py @@ -9,12 +9,10 @@ class ASMIprobe(Module): assert(trace_depth < 256) assert(slot_count < 256) - self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._slot_status = [RegisterField("slot_status" + str(i), 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - for i in range(slot_count)] - self._trace = [RegisterField("trace" + str(i), 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - for i in range(trace_depth)] + self._slot_count = RegisterField(8, READ_ONLY, WRITE_ONLY) + self._trace_depth = RegisterField(8, READ_ONLY, WRITE_ONLY) + self._slot_status = [RegisterField(2, READ_ONLY, WRITE_ONLY, name="slot_status" + str(i)) for i in range(slot_count)] + self._trace = [RegisterField(8, READ_ONLY, WRITE_ONLY, name="trace" + str(i)) for i in range(trace_depth)] ### diff --git a/milkymist/dfii/__init__.py b/milkymist/dfii/__init__.py index dc71c820..06b08e29 100644 --- a/milkymist/dfii/__init__.py +++ b/milkymist/dfii/__init__.py @@ -5,21 +5,20 @@ from migen.bank.description import * class PhaseInjector(Module, AutoReg): def __init__(self, phase): - self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY) - self._we = Field("we", 1, WRITE_ONLY, READ_ONLY) - self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY) - self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY) - self._wren = Field("wren", 1, WRITE_ONLY, READ_ONLY) - self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY) - self._command = RegisterFields("command", - [self._cs, self._we, self._cas, self._ras, self._wren, self._rden]) - self._command_issue = RegisterRaw("command_issue") + self._cs = Field(1, WRITE_ONLY, READ_ONLY) + self._we = Field(1, WRITE_ONLY, READ_ONLY) + self._cas = Field(1, WRITE_ONLY, READ_ONLY) + self._ras = Field(1, WRITE_ONLY, READ_ONLY) + self._wren = Field(1, WRITE_ONLY, READ_ONLY) + self._rden = Field(1, WRITE_ONLY, READ_ONLY) + self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden) + self._command_issue = RegisterRaw() - self._address = RegisterField("address", len(phase.address)) - self._baddress = RegisterField("baddress", len(phase.bank)) + self._address = RegisterField(len(phase.address)) + self._baddress = RegisterField(len(phase.bank)) - self._wrdata = RegisterField("wrdata", len(phase.wrdata)) - self._rddata = RegisterField("rddata", len(phase.rddata), READ_ONLY, WRITE_ONLY) + self._wrdata = RegisterField(len(phase.wrdata)) + self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY) ### @@ -50,9 +49,9 @@ class DFIInjector(Module, AutoReg): self.slave = dfi.Interface(a, ba, d, nphases) self.master = dfi.Interface(a, ba, d, nphases) - self._sel = Field("sel") - self._cke = Field("cke") - self._control = RegisterFields("control", [self._sel, self._cke]) + self._sel = Field() + self._cke = Field() + self._control = RegisterFields(self._sel, self._cke) for n, phase in enumerate(inti.phases): setattr(self.submodules, "pi" + str(n), PhaseInjector(phase)) diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py index f0b6b1c3..bedc603a 100644 --- a/milkymist/framebuffer/__init__.py +++ b/milkymist/framebuffer/__init__.py @@ -6,7 +6,6 @@ from migen.flow.network import * from migen.flow.transactions import * from migen.flow import plumbing from migen.actorlib import misc, dma_asmi, structuring, sim, spi -from migen.bank.description import * _hbits = 11 _vbits = 11 diff --git a/milkymist/identifier/__init__.py b/milkymist/identifier/__init__.py index 8d56f27c..b6b4ed97 100644 --- a/milkymist/identifier/__init__.py +++ b/milkymist/identifier/__init__.py @@ -17,9 +17,9 @@ def encode_version(version): class Identifier(Module, AutoReg): def __init__(self, sysid, version, frequency): - self._r_sysid = RegisterField("sysid", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._r_version = RegisterField("version", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._r_frequency = RegisterField("frequency", 32, access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY) ### diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py index cdbdf45e..893ae374 100644 --- a/milkymist/minimac3/__init__.py +++ b/milkymist/minimac3/__init__.py @@ -23,11 +23,11 @@ class MiniMAC(Module, AutoReg): self.phy_rst_n = Signal() # CPU interface - self._phy_reset = RegisterField("phy_reset", reset=1) - self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE) - self._tx_start = RegisterRaw("tx_start") + self._phy_reset = RegisterField(reset=1) + self._rx_count_0 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._rx_count_1 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._tx_count = RegisterField(_count_width, access_dev=READ_WRITE) + self._tx_start = RegisterRaw() self.submodules.ev = EventManager() self.ev.rx0 = EventSourcePulse() diff --git a/milkymist/timer/__init__.py b/milkymist/timer/__init__.py index be51d33a..810cd74b 100644 --- a/milkymist/timer/__init__.py +++ b/milkymist/timer/__init__.py @@ -5,9 +5,9 @@ from migen.bank.eventmanager import * class Timer(Module, AutoReg): def __init__(self, width=32): - self._en = RegisterField("en") - self._value = RegisterField("value", width, access_dev=READ_WRITE) - self._reload = RegisterField("reload", width) + self._en = RegisterField() + self._value = RegisterField(width, access_dev=READ_WRITE) + self._reload = RegisterField(width) self.submodules.ev = EventManager() self.ev.zero = EventSourceLevel() diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py index d1eca795..8dd903f0 100644 --- a/milkymist/uart/__init__.py +++ b/milkymist/uart/__init__.py @@ -6,8 +6,8 @@ from migen.bank.eventmanager import * class UART(Module, AutoReg): def __init__(self, clk_freq, baud=115200): - self._rxtx = RegisterRaw("rxtx", 8) - self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16)) + self._rxtx = RegisterRaw(8) + self._divisor = RegisterField(16, reset=int(clk_freq/baud/16)) self.submodules.ev = EventManager() self.ev.tx = EventSourceLevel()