From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 7 Jan 2021 17:25:48 +0000 (+0100)
Subject: set initial_sprs, cleanup mfspr testprog
X-Git-Tag: 24jan2021_ls180~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a24744139025cce94eab543241c12d27a37b7f85;hp=179c6f905aa3e5dbfc717604446be78735d719e6;p=soc.git

set initial_sprs, cleanup mfspr testprog
---

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index 71aae015..e45b3065 100644
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -77,15 +77,14 @@ class MMUTestCase(TestAccumulatorBase):
 
     def case_mfspr_after_invalid_load(self):
         lst = [ # TODO -- set SPR on both sinulator and port interface
-                "mfspr 1, 18", # DSISR to reg 1 -- KeyError: 2 in simulator
-                "mfspr 2, 19", # DAR to reg 2   -- with key = spr_dict[key].SPR
+                "mfspr 1, 18", # DSISR to reg 1
+                "mfspr 2, 19", # DAR to reg 2
                 # TODO -- verify returned sprvals
               ]
 
         initial_regs = [0] * 32
 
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
-                        'XER': 0xe00c0000}
+        initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs)