From: Florent Kermarrec Date: Tue, 23 Apr 2019 08:51:36 +0000 (+0200) Subject: targets/xilinx: remove keep attribute on clock going to idelayctrl X-Git-Tag: 24jan2021_ls180~1291 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a24bf72fc7ac6c1e5e46f807ab3366a31b38f54a;p=litex.git targets/xilinx: remove keep attribute on clock going to idelayctrl Causes P&R issues with Vivado. --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index c6e90e45..ba058c5f 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -31,7 +31,6 @@ class _CRG(Module): self.cd_sys.clk.attr.add("keep") self.cd_sys4x.clk.attr.add("keep") self.cd_sys4x_dqs.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 7c8c331b..efd73979 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -29,7 +29,6 @@ class _CRG(Module): self.cd_sys.clk.attr.add("keep") self.cd_sys4x.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 3ad91e76..14b53239 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -29,7 +29,6 @@ class _CRG(Module): self.cd_sys.clk.attr.add("keep") self.cd_sys4x.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index d676cff3..06eda9e2 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -30,8 +30,6 @@ class _CRG(Module): self.cd_sys.clk.attr.add("keep") self.cd_sys4x.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") - self.cd_ic.clk.attr.add("keep") self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 661aba18..5adf51d8 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -23,15 +23,12 @@ class _CRG(Module): self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_clk100 = ClockDomain() # # # self.cd_sys.clk.attr.add("keep") self.cd_sys2x.clk.attr.add("keep") self.cd_sys2x_dqs.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") - self.cd_clk100.clk.attr.add("keep") self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) @@ -40,7 +37,6 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) - pll.create_clkout(self.cd_clk100, 100e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 1e58f831..d949f57a 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -32,8 +32,6 @@ class _CRG(Module): self.cd_sys.clk.attr.add("keep") self.cd_sys4x.clk.attr.add("keep") self.cd_sys4x_dqs.clk.attr.add("keep") - self.cd_clk200.clk.attr.add("keep") - self.cd_clk100.clk.attr.add("keep") self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) @@ -42,7 +40,6 @@ class _CRG(Module): pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) - pll.create_clkout(self.cd_clk100, 100e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)