From: Wesley W. Terpstra <wesley@sifive.com>
Date: Wed, 26 Apr 2017 20:10:50 +0000 (-0700)
Subject: axi4: switch to new pipelined converters
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a24fa9b444c3e33e356e83dba07572b26098f17e;p=sifive-blocks.git

axi4: switch to new pipelined converters
---

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 0ea057f..c248f6c 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -28,16 +28,21 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),
-      supportsRead  = TransferSizes(1, 256*8),
-      interleavedId = Some(0))),
+      supportsRead  = TransferSizes(1, 256*8))),
     beatBytes = 8)))
 
-  val xing = LazyModule(new TLAsyncCrossing)
-  val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+  val xing    = LazyModule(new TLAsyncCrossing)
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8))
+  val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+  val yank    = LazyModule(new AXI4UserYanker)
 
   xing.node := node
   val monitor = (toaxi4.node := xing.node)
-  axi4 := toaxi4.node
+  axi4 := yank.node
+  yank.node := deint.node
+  deint.node := indexer.node
+  indexer.node := toaxi4.node
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -80,9 +85,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     xing.module.io.in_reset := reset
     xing.module.io.out_clock := blackbox.io.ui_clk
     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
-    toaxi4.module.clock := blackbox.io.ui_clk
-    toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
-    monitor.foreach { lm =>
+    (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
       lm.module.clock := blackbox.io.ui_clk
       lm.module.reset := blackbox.io.ui_clk_sync_rst
     }
diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index f657459..2e376d0 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -26,9 +26,31 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val intnode = IntOutputNode()
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
-  axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
-  axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
-  master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+
+  axi_to_pcie_x1.slave :=
+    AXI4Buffer()(
+    AXI4UserYanker()(
+    AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
+    AXI4IdIndexer(idBits=4)(
+    TLToAXI4(beatBytes=8)(
+    slave)))))
+
+  axi_to_pcie_x1.control :=
+    AXI4Buffer()(
+    AXI4UserYanker()(
+    AXI4Fragmenter()(
+    AXI4IdIndexer(idBits=0)(
+    TLToAXI4(beatBytes=4)(
+    control)))))
+
+  master :=
+    TLWidthWidget(8)(
+    AXI4ToTL()(
+    AXI4UserYanker(capMaxFlight=Some(8))(
+    AXI4Fragmenter()(
+    AXI4IdIndexer(idBits=0)(
+    axi_to_pcie_x1.master)))))
+
   intnode := axi_to_pcie_x1.intnode
 
   lazy val module = new LazyModuleImp(this) {
diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index b4fad21..d9ffe8b 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -197,8 +197,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       resources     = Seq(Resource(device, "ranges")),
       executable    = true,
       supportsWrite = TransferSizes(1, 256),
-      supportsRead  = TransferSizes(1, 256),
-      interleavedId = Some(0))), // the Xilinx IP is friendly
+      supportsRead  = TransferSizes(1, 256))),
     beatBytes = 8)))
 
   val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
@@ -206,8 +205,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       resources     = device.reg,
       supportsWrite = TransferSizes(1, 4),
-      supportsRead  = TransferSizes(1, 4),
-      interleavedId = Some(0))), // no read interleaving b/c AXI-lite
+      supportsRead  = TransferSizes(1, 4))),
     beatBytes = 4)))
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(