From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 22 Nov 2020 20:19:56 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1684
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a280bf925ca9d7a317d9ac68c9cc71065ed776de;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 99f6a5d8e..1cdd0e7e2 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -30,12 +30,31 @@ If you violate any of the above stated hard-and-fast rules you will end up learn
 |         | Ensure there are **ZERO** wires connected to either the FPGA or the STLINKv2, there should not even be a usb, mirco-usb, or power cable anywhere these components |
 |         | Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page |
 |         | Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page |
+
+Follow this section if you have the ULX3S FPGA:
+
+| Done?   | Checklist Step |
+|---------|----------------|
 |         | Wire the **RED** jumper cable to (**ULX3S pin #2**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) |
 |         | Wire the **BLACK** jumper cable to (**ULX3S pin #4**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
 |         | Wire the **GREEN** jumper cable to (**ULX3S pin #5**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
 |         | Wire the **BLUE** jumper cable to (**ULX3S pin #6**) then wire it to (**STLINKv2 pin#7**), this will serve as the **Test Mode Select** signal (**TMS**) |
 |         | Wire the **WHITE** jumper cable to (**ULX3S pin #7**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
 |         | Wire the **YELLOW** jumper cable to (**ULX3S pin #8**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
+
+Follow this section if you have the Versa ECP5 FPGA:
+
+| Done?   | Checklist Step |
+|---------|----------------|
+|         | Wire the **RED** jumper cable to (**X3 pin #39**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) |
+|         | Wire the **BLACK** jumper cable to (**X3 pin #1**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
+|         | Wire the **GREEN** jumper cable to (**X3 pin #4**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
+|         | Wire the **BLUE** jumper cable to (**X3 pin #5**) then wire it to (**STLINKv2 pin#7**), this will serve as the **Test Mode Select** signal (**TMS**) |
+|         | Wire the **WHITE** jumper cable to (**X3 pin #6**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
+|         | Wire the **YELLOW** jumper cable to (**X3 pin #7**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
+
+Final steps for both FPGA boards:
+
 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **four** times |
 |         | I don't know what's next, need to review with lkcl |