From: Luke Kenneth Casson Leighton Date: Sat, 15 Jun 2019 07:41:48 +0000 (+0100) Subject: convert addr match into latched (SRLatch) version, activate on req_rel, X-Git-Tag: div_pipeline~1851 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2841b8e2ae4155127148894c9f6b1a8168ef016;p=soc.git convert addr match into latched (SRLatch) version, activate on req_rel, deactivate on busy --- diff --git a/src/experiment/alu_hier.py b/src/experiment/alu_hier.py index 9c753005..8e3677a5 100644 --- a/src/experiment/alu_hier.py +++ b/src/experiment/alu_hier.py @@ -102,10 +102,10 @@ class ALU(Elaboratable): m.d.sync += self.counter.eq(5) with m.Elif(self.op == 3): # SHIFT to take 7 m.d.sync += self.counter.eq(7) - with m.Elif(self.op == 1): # SUB to take 2 - m.d.sync += self.counter.eq(2) - with m.Else(): # ADD to take 1, straight away + with m.Elif(self.op == 1): # SUB to take 1, straight away m.d.sync += self.counter.eq(1) + with m.Else(): # ADD to take 2 + m.d.sync += self.counter.eq(2) m.d.comb += go_now.eq(1) with m.Else(): # input says no longer valid, so drop ready as well. diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index ed953e8b..e6918133 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -114,6 +114,7 @@ class CompUnitsBase(Elaboratable): self.go_die_i = Signal(n_units, reset_less=True) if ldstmode: self.go_ad_i = Signal(n_units, reset_less=True) + self.go_st_i = Signal(n_units, reset_less=True) # outputs self.busy_o = Signal(n_units, reset_less=True) @@ -183,6 +184,7 @@ class CompUnitsBase(Elaboratable): ldmem_l = [] stmem_l = [] go_ad_l = [] + go_st_l = [] adr_rel_l = [] sto_rel_l = [] for alu in self.units: @@ -191,11 +193,13 @@ class CompUnitsBase(Elaboratable): ldmem_l.append(alu.load_mem_o) stmem_l.append(alu.stwd_mem_o) go_ad_l.append(alu.go_ad_i) + go_st_l.append(alu.go_st_i) comb += self.adr_rel_o.eq(Cat(*adr_rel_l)) comb += self.sto_rel_o.eq(Cat(*sto_rel_l)) comb += self.load_mem_o.eq(Cat(*ldmem_l)) comb += self.stwd_mem_o.eq(Cat(*stmem_l)) comb += Cat(*go_ad_l).eq(self.go_ad_i) + comb += Cat(*go_st_l).eq(self.go_st_i) return m @@ -538,10 +542,18 @@ class Scoreboard(Elaboratable): #--------- comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs comb += memfus.addr_we_i.eq(cul.adr_rel_o) # Match enable on adr rel + comb += memfus.addr_rs_i.eq(~cul.busy_o) # Match disable on busy off + # connect up address data comb += memfus.addrs_i[0].eq(cul.units[0].data_o) comb += memfus.addrs_i[1].eq(cul.units[1].data_o) + # connect loadable / storable to go_ld/go_st. + # XXX should only be done when the memory ld/st has actually happened! + + #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_match_o) + #comb += cul.go_st_i.eq(memfus.storable_o & memfus.addr_match_o) + #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus]) #comb += cu.issue_i[0:n_intfus].eq(fn_issue_o[0:n_intfus]) @@ -1106,8 +1118,9 @@ def scoreboard_sim(dut, alusim): if False: instrs = create_random_ops(dut, 15, True, 4) - if True: # LD test (with immediate) - instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) ) + if True: # LD/ST test (with immediate) + instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) ) + #instrs.append( (5, 6, 7, 0x10, 1, 1, (0, 0)) ) if False: instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) ) diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py index a042e0df..bad7c78f 100644 --- a/src/scoreboard/addr_match.py +++ b/src/scoreboard/addr_match.py @@ -32,7 +32,7 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Const, Array, Cat, Elaboratable -from nmutil.latch import latchregister +from nmutil.latch import latchregister, SRLatch class PartialAddrMatch(Elaboratable): @@ -44,7 +44,8 @@ class PartialAddrMatch(Elaboratable): # inputs self.addrs_i = Array(Signal(bitwid, name="addr") for i in range(n_adr)) self.addr_we_i = Signal(n_adr) # write-enable for incoming address - self.addr_en_i = Signal(n_adr) # address activated (0 == ignore) + self.addr_en_i = Signal(n_adr) # address latched in + self.addr_rs_i = Signal(n_adr) # address deactivated # output self.addr_match_o = Array(Signal(n_adr, name="match_o") \ @@ -58,23 +59,26 @@ class PartialAddrMatch(Elaboratable): comb = m.d.comb sync = m.d.sync + m.submodules.l = l = SRLatch(llen=self.n_adr, sync=False) addrs_r = Array(Signal(self.bitwid, "a_r") for i in range(self.n_adr)) - ae_r = Signal(self.n_adr) + + # latch set/reset + comb += l.s.eq(self.addr_en_i) + comb += l.r.eq(self.addr_rs_i) # copy in addresses (and "enable" signals) for i in range(self.n_adr): - latchregister(m, self.addrs_i[i], addrs_r[i], self.addr_we_i[i]) - latchregister(m, self.addr_en_i[i], ae_r[i], self.addr_we_i[i]) + latchregister(m, self.addrs_i[i], addrs_r[i], l.q[i]) # is there a clash, yes/no for i in range(self.n_adr): - match = [] + nomatch = [] for j in range(self.n_adr): if i == j: - match.append(Const(0)) # don't match against self! + nomatch.append(Const(1)) # don't match against self! else: - match.append(addrs_r[i] == addrs_r[j]) - comb += self.addr_match_o[i].eq(Cat(*match) & ae_r) + nomatch.append(addrs_r[i] != addrs_r[j]) + comb += self.addr_match_o[i].eq(Cat(*nomatch) & l.q) return m diff --git a/src/scoreboard/memfu.py b/src/scoreboard/memfu.py index 472ad9d1..8173acec 100644 --- a/src/scoreboard/memfu.py +++ b/src/scoreboard/memfu.py @@ -23,6 +23,7 @@ class MemFunctionUnits(Elaboratable): self.loadable_o = Signal(n_ldsts, reset_less=True) self.storable_o = Signal(n_ldsts, reset_less=True) + #self.addr_match_o = Signal(n_ldsts, reset_less=True) self.go_ld_i = Signal(n_ldsts, reset_less=True) self.go_st_i = Signal(n_ldsts, reset_less=True) @@ -33,7 +34,8 @@ class MemFunctionUnits(Elaboratable): self.addrs_i = Array(Signal(self.bitwid, name="addrs_i%d" % i) \ for i in range(n_ldsts)) self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address - self.addr_en_i = Signal(n_ldsts) # address activated (0 == ignore) + self.addr_en_i = Signal(n_ldsts) # address latched in + self.addr_rs_i = Signal(n_ldsts) # address deactivated # Note: FURegs st_pend_o is also outputted from here, for use in WaWGrid @@ -74,6 +76,7 @@ class MemFunctionUnits(Elaboratable): comb += intfudeps.go_die_i.eq(self.go_die_i) comb += self.loadable_o.eq(intfudeps.readable_o) comb += self.storable_o.eq(intfudeps.writable_o) + #comb += self.addr_match_o.eq(intregdeps.addr_match_o) # Connect function issue / arrays, and dest/src1/src2 comb += intregdeps.dest_i.eq(self.st_i) @@ -92,6 +95,7 @@ class MemFunctionUnits(Elaboratable): comb += intregdeps.addrs_i[i].eq(self.addrs_i[i]) comb += intregdeps.addr_we_i.eq(self.addr_we_i) comb += intregdeps.addr_en_i.eq(self.addr_en_i) + comb += intregdeps.addr_rs_i.eq(self.addr_rs_i) return m