From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 12 Feb 2019 17:21:15 +0000 (-0800)
Subject: Use module->add{Not,And}Gate() functions
X-Git-Tag: yosys-0.9~232^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2ae39381124ccfec348293c7c7926597c26a5b8;p=yosys.git

Use module->add{Not,And}Gate() functions
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c45de8531..888a4afe6 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -134,9 +134,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
     }
 
     log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-    RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
-    inv->setPort("\\A", wire_inv);
-    inv->setPort("\\Y", wire);
+    module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
 
     return wire;
 }
@@ -236,11 +234,7 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
         RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
         RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-
-        RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-        and_cell->setPort("\\A", i1_wire);
-        and_cell->setPort("\\B", i2_wire);
-        and_cell->setPort("\\Y", o_wire);
+        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
     }
     std::getline(f, line); // Ignore up to start of next line
 }