From: Cole Poirier <colepoirier@gmail.com>
Date: Sat, 29 Aug 2020 22:41:07 +0000 (-0700)
Subject: mem_types add more types from common.vhdl specifially for icache,
X-Git-Tag: semi_working_ecp5~229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2c091505f1aa8037d59f07777851d124330df84;p=soc.git

mem_types add more types from common.vhdl specifially for icache,
Fetch1ToIcacheType() and IcacheToDecode1Type()
---

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index 95d1bf1f..ed7b411f 100644
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -25,6 +25,25 @@ class DcacheToMmuType(RecordObject):
         self.err           = Signal()
         self.data          = Signal(64)
 
+class Fetch1ToIcacheType(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.req           = Signal()
+        self.virt_mode     = Signal()
+        self.priv_mode     = Signal()
+        self.stop_mark     = Signal()
+        self.sequential    = Signal()
+        self.nia           = Signal(64)
+
+class IcacheToDecode1Type(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.valid         = Signal()
+        self.stop_mark     = Signal()
+        self.fetch_failed  = Signal()
+        self.nia           = Signal(64)
+        self.insn          = Signal(32)
+
 class LoadStore1ToDcacheType(RecordObject):
     def __init__(self):
         super().__init__()