From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 18:18:57 +0000 (+0100)
Subject: test 32/64 bit mode CTR in branch
X-Git-Tag: div_pipeline~1097
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2d03c14aa22717f71b3614bc93dfcaf4485e773;p=soc.git

test 32/64 bit mode CTR in branch
---

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index d917a5d7..6f6d488a 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -82,13 +82,20 @@ class BranchMainStage(PipeModBase):
         with m.If(BO[2]):
             comb += bc_taken.eq((cr_bit == BO[3]) | BO[4])
         with m.Else():
-            # Yes, the CTR only counts 32 bits
+            # decrement the counter and place into output
             ctr = Signal(64, reset_less=True)
             comb += ctr.eq(self.i.ctr - 1)
             comb += self.o.ctr.data.eq(ctr)
             comb += self.o.ctr.ok.eq(1)
+            # take either all 64 bits or only 32 of post-incremented counter
+            ctr_m = Signal(64, reset_less=True)
+            with m.If((op.is_32bit):
+                comb += ctr_m.eq(ctr[:32])
+            with m.Else():
+                comb += ctr_m.eq(ctr)
+            # check CTR zero/non-zero against BO[1]
             ctr_zero_bo1 = Signal(reset_less=True) # BO[1] == (ctr==0)
-            comb += ctr_zero_bo1.eq(BO[1] ^ ctr.any())
+            comb += ctr_zero_bo1.eq(BO[1] ^ ctr_m.any())
             with m.If(BO[3:5] == 0b00):
                 comb += bc_taken.eq(ctr_zero_bo1 & ~cr_bit)
             with m.Elif(BO[3:5] == 0b01):