From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 4 Dec 2013 08:24:52 +0000 (+0100)
Subject: Fix in sincos testbench gen
X-Git-Tag: yosys-0.2.0~263
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2d053694b6269bab8871a810142943fac6a3a18;p=yosys.git

Fix in sincos testbench gen
---

diff --git a/tests/simple/sincos.v b/tests/simple/sincos.v
index 66156b685..b3124337d 100644
--- a/tests/simple/sincos.v
+++ b/tests/simple/sincos.v
@@ -39,7 +39,7 @@ input start;
 input clock;
 input reset;
 
-(* gentb_constant="0" *)
+(* gentb_constant = 1'b0 *)
 wire reset;
 
 always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR