From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 21:50:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1748
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2d257cd351ae0bd33abf6d8c35fdbe48671e794;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 87f8080e4..4c270feb1 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -172,8 +172,21 @@ is to be considered as if the "single element".  Caveats exist for
 
 Registers used as Predicate Masks must *never* be altered by *any*
 instruction when Vertical-First is active.  If more than the available
-predicate registers are required (r3, r10, r30, CR Fields) then
-a simple branch-conditional test should be used instead.
+predicate registers are required (r3, r10, r30, CR Predicate Fields) then
+because Vertical-First is not that different from executing standard
+Scalar instructions,
+a simple branch-conditional test should be used instead of predication,
+exactly as would normally be done if SVP64 was not in use.
+
+These rules allow Hardware implementors to choose to
+free up the connection
+between registers used as predicates and registers used for standard
+purposes: Hazards need not be created.
+
+Note that each of the registers may each be used as predicates,
+or they may be used for standard normal purposes. If mixed for
+both purposes when Vertical-First is active, the results of execution
+is `UNDEFINED`.
 
 # Pseudocode
 
@@ -189,7 +202,7 @@ a simple branch-conditional test should be used instead.
     if vf and not vs and not ms {
         // increment src/dest step mode
         // NOTE! this is in no way complete! predication is not included
-        // and neither is SUB-VL mode
+        // and neither is SUBVL mode
         srcstep = SPR[SV].srcstep
         dststep = SPR[SV].dststep
         VL = SPR[SV].VL
@@ -206,7 +219,7 @@ a simple branch-conditional test should be used instead.
 
         // write CR? helps for doing Vertical loops, detects end
         // of Vector Elements
-        if Rc {
+        if Rc = 1 {
             // update CR to indicate that srcstep/dststep "rolled over"
             CR0.eq = rollover
         }
@@ -253,7 +266,7 @@ a simple branch-conditional test should be used instead.
             regs[rt] = VL;
         }
         // write CR?
-        if Rc {
+        if Rc = 1 {
             // update CR from VL (not rt)
             CR0.eq = (VL == 0)
             ...