From: lkcl <lkcl@web>
Date: Mon, 28 Jun 2021 09:00:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~703
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2d882cbce245f74c9a9cdc7ac232e070184ebac;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index c2230125b..741a9da27 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -9,6 +9,7 @@ See links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
+* old page [[simple_v_extension/specification/sv.setvl]]
 
 Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]♧