From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 12 Nov 2019 03:33:49 +0000 (-0500)
Subject: nir/serialize: serialize writemask for vec8 and vec16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2df670b1419296060d6914eb9a930171a38092c;p=mesa.git

nir/serialize: serialize writemask for vec8 and vec16

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
---

diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c
index 8877fc81ae7..c64acfe3f18 100644
--- a/src/compiler/nir/nir_serialize.c
+++ b/src/compiler/nir/nir_serialize.c
@@ -806,6 +806,7 @@ static void
 write_alu(write_ctx *ctx, const nir_alu_instr *alu)
 {
    unsigned num_srcs = nir_op_infos[alu->op].num_inputs;
+   unsigned dst_components = nir_dest_num_components(alu->dest.dest);
 
    /* 9 bits for nir_op */
    STATIC_ASSERT(nir_num_opcodes <= 512);
@@ -826,13 +827,16 @@ write_alu(write_ctx *ctx, const nir_alu_instr *alu)
       header.alu.writemask_or_two_swizzles = alu->src[0].swizzle[0];
       if (num_srcs > 1)
          header.alu.writemask_or_two_swizzles |= alu->src[1].swizzle[0] << 2;
-   } else if (!alu->dest.dest.is_ssa) {
-      /* For registers, this field is a writemask. */
+   } else if (!alu->dest.dest.is_ssa && dst_components <= 4) {
+      /* For vec4 registers, this field is a writemask. */
       header.alu.writemask_or_two_swizzles = alu->dest.write_mask;
    }
 
    write_dest(ctx, &alu->dest.dest, header, alu->instr.type);
 
+   if (!alu->dest.dest.is_ssa && dst_components > 4)
+      blob_write_uint32(ctx->blob, alu->dest.write_mask);
+
    if (header.alu.packed_src_ssa_16bit) {
       for (unsigned i = 0; i < num_srcs; i++) {
          assert(alu->src[i].src.is_ssa);
@@ -888,6 +892,16 @@ read_alu(read_ctx *ctx, union packed_instr header)
 
    read_dest(ctx, &alu->dest.dest, &alu->instr, header);
 
+   unsigned dst_components = nir_dest_num_components(alu->dest.dest);
+
+   if (alu->dest.dest.is_ssa) {
+      alu->dest.write_mask = u_bit_consecutive(0, dst_components);
+   } else if (dst_components <= 4) {
+      alu->dest.write_mask = header.alu.writemask_or_two_swizzles;
+   } else {
+      alu->dest.write_mask = blob_read_uint32(ctx->blob);
+   }
+
    if (header.alu.packed_src_ssa_16bit) {
       for (unsigned i = 0; i < num_srcs; i++) {
          nir_alu_src *src = &alu->src[i];
@@ -930,13 +944,6 @@ read_alu(read_ctx *ctx, union packed_instr header)
       }
    }
 
-   if (alu->dest.dest.is_ssa) {
-      alu->dest.write_mask =
-         u_bit_consecutive(0, alu->dest.dest.ssa.num_components);
-   } else {
-      alu->dest.write_mask = header.alu.writemask_or_two_swizzles;
-   }
-
    if (header.alu.packed_src_ssa_16bit &&
        alu->dest.dest.is_ssa) {
       alu->src[0].swizzle[0] = header.alu.writemask_or_two_swizzles & 0x3;