From: Giacomo Travaglini Date: Tue, 23 Jan 2018 11:19:50 +0000 (+0000) Subject: arch-arm: Implement missing aarch32 TLBI registers X-Git-Tag: v19.0.0.0~2243 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2df8b2f631b82b2830a64206fe50acbf12e7940;p=gem5.git arch-arm: Implement missing aarch32 TLBI registers In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels. Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d6992dc44..4d27c9a22 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1062,8 +1062,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el); return; // TLBI based on VA, EL0&1 inner sharable (ignored) - case MISCREG_TLBIMVAIS: + case MISCREG_TLBIMVAL: + case MISCREG_TLBIMVALIS: + // mcr tlbimval(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVA: + case MISCREG_TLBIMVAIS: assert32(tc); target_el = 1; // el 0 and 1 are handled together scr = readMiscReg(MISCREG_SCR, tc); @@ -1111,8 +1116,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } return; // TLBI by address, EL0&1, inner sharable (ignored) - case MISCREG_TLBIMVAAIS: + case MISCREG_TLBIMVAAL: + case MISCREG_TLBIMVAALIS: + // mcr tlbimvaal(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVAA: + case MISCREG_TLBIMVAAIS: assert32(tc); target_el = 1; // el 0 and 1 are handled together scr = readMiscReg(MISCREG_SCR, tc); @@ -1121,6 +1131,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); return; // TLBI by address, EL2, hypervisor mode + case MISCREG_TLBIMVALH: + case MISCREG_TLBIMVALHIS: + // mcr tlbimvalh(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVAH: case MISCREG_TLBIMVAHIS: assert32(tc); diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 7d5441ca8..5a1ef5a6a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -444,6 +444,10 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_TLBIASIDIS; case 3: return MISCREG_TLBIMVAAIS; + case 5: + return MISCREG_TLBIMVALIS; + case 7: + return MISCREG_TLBIMVAALIS; } break; case 5: @@ -476,6 +480,10 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_TLBIASID; case 3: return MISCREG_TLBIMVAA; + case 5: + return MISCREG_TLBIMVAL; + case 7: + return MISCREG_TLBIMVAAL; } break; } @@ -488,6 +496,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_TLBIMVAHIS; case 4: return MISCREG_TLBIALLNSNHIS; + case 5: + return MISCREG_TLBIMVALHIS; } } else if (crm == 7) { switch (opc2) { @@ -497,6 +507,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_TLBIMVAH; case 4: return MISCREG_TLBIALLNSNH; + case 5: + return MISCREG_TLBIMVALH; } } } @@ -2892,10 +2904,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVAAIS) .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIMVALIS) - .unimplemented() .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIMVAALIS) - .unimplemented() .writes(1).exceptUserMode(); InitReg(MISCREG_ITLBIALL) .writes(1).exceptUserMode(); @@ -2918,10 +2928,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVAA) .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIMVAL) - .unimplemented() .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIMVAAL) - .unimplemented() .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIIPAS2IS) .unimplemented() @@ -2936,7 +2944,6 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIALLNSNHIS) .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIMVALHIS) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2) .unimplemented() @@ -2951,7 +2958,6 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIALLNSNH) .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIMVALH) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_PMCR) .allPrivileges(); diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 4e99d980e..c272ef624 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -464,6 +464,8 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, case MISCREG_TLBIMVAIS: case MISCREG_TLBIASIDIS: case MISCREG_TLBIMVAAIS: + case MISCREG_TLBIMVALIS: + case MISCREG_TLBIMVAALIS: case MISCREG_DTLBIALL: case MISCREG_ITLBIALL: case MISCREG_DTLBIMVA: @@ -473,6 +475,8 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, case MISCREG_TLBIMVAA: case MISCREG_TLBIALL: case MISCREG_TLBIMVA: + case MISCREG_TLBIMVAL: + case MISCREG_TLBIMVAAL: case MISCREG_TLBIASID: trapToHype = hcr.ttlb; break;