From: lkcl <lkcl@web>
Date: Wed, 16 Dec 2020 08:42:48 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1292
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2e29b8c159c77bc58210b5cfa8e9cbc498693c5;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 5f0a83925..525095124 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -61,7 +61,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | ELWIDTH_SRC                  | `17:18`    | Element Width for Source (only on instructions with twin-predication)     |
 | MODE                          | `19:23`    | see [[discussion]]                                                                       |
 
-note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added.
+note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added.  conclusion: no.  2nd SUBVL makes no sense except for mv, and that is covered by [[mv.vec]]
 
 ## R\*_EXTRA Encoding