From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 14 Sep 2020 13:46:53 +0000 (+0100)
Subject: rename plru input
X-Git-Tag: semi_working_ecp5~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2e4bce6906fb70146dcb2aafbf4e42a33d264d4;p=soc.git

rename plru input
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index a95e2842..e377b3a9 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -26,7 +26,8 @@ from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS,
                                 WBIOMasterOut, WBIOSlaveOut)
 
 from soc.experiment.cache_ram import CacheRam
-from soc.experiment.plru import PLRU
+#from soc.experiment.plru import PLRU
+from nmutil.plru import PLRU
 
 # for test
 from nmigen_soc.wishbone.sram import SRAM