From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 3 May 2018 00:01:39 +0000 (-0400)
Subject: ac/gpu_info: add has_read_registers_query
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2e9d9b4c199ff1b53a625a345e566200016e2d9;p=mesa.git

ac/gpu_info: add has_read_registers_query

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 906e76ba051..3442ffa6259 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -338,6 +338,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		info->chip_class >= CIK && info->chip_class <= VI &&
 		info->drm_minor >= 13;
 	info->has_2d_tiling = true;
+	info->has_read_registers_query = true;
 
 	info->num_render_backends = amdinfo->rb_pipes;
 	/* The value returned by the kernel driver was wrong. */
@@ -498,6 +499,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
 	printf("    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
 	printf("    has_2d_tiling = %u\n", info->has_2d_tiling);
+	printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index fb44f7c8af4..1201d811361 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -109,6 +109,7 @@ struct radeon_info {
 	bool                        has_unaligned_shader_loads;
 	bool                        has_sparse_vm_mappings;
 	bool                        has_2d_tiling;
+	bool                        has_read_registers_query;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index b7d40db21cb..36cbb8866ed 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -294,9 +294,8 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
 
 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
 {
-	if (sctx->screen->info.drm_major == 2 &&
-	    sctx->screen->info.drm_minor < 42)
-		return; /* no radeon support */
+	if (!sctx->screen->info.has_read_registers_query)
+		return;
 
 	fprintf(f, "Memory-mapped registers:\n");
 	si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index cb8c7ce9fcb..76eea67521d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -550,6 +550,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_sparse_vm_mappings = false;
     /* 2D tiling on CIK is supported since DRM 2.35.0 */
     ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
+    ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;