From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 00:56:38 +0000 (-0700)
Subject: abc -> abc9
X-Git-Tag: working-ls180~881^2^2~180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2ef93f03a1f75c25329c66d0e7d69da71e88e1f;p=yosys.git

abc -> abc9
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c598acf2..07f3d9a8a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass
 							"will use timing for 'xc7' instead.\n", family.c_str());
 				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
-				std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
+				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
 				abc9_opts += " -nomfs";
 				if (nowidelut)
-					abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
+					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
-					abc9_opts += " -lut +/xilinx/abc_xc7.lut";
+					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
 			}
 			else {