From: Mike Frysinger Date: Tue, 5 Jan 2021 05:22:28 +0000 (-0500) Subject: sim: h8300: fix test mach markers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2f8e947a8457341d2d82b555ff739839cb8de1f;p=binutils-gdb.git sim: h8300: fix test mach markers These tests all fail to assemble when targeting the h8300 or h8300h cpu variants with errors like: rotl.s:242: Warning: Opcode `rotl.b' with these operand types not available in H8/300H mode rotl.s:242: Error: invalid operands It's been this way for years and no one seems to care, so disable them for those targets since the assembler thinks it's impossible. --- diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index a4e7532352b..82128cc43ad 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,3 +1,9 @@ +2021-01-05 Mike Frysinger + + * rotl.s (mach): Set to "h8300s h8sx". + * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: + Likewise. + 2021-01-05 Mike Frysinger * allinsn.exp: Rewrite file to use globs. diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s index 088345d3df7..1978c2d5572 100644 --- a/sim/testsuite/sim/h8300/rotl.s +++ b/sim/testsuite/sim/h8300/rotl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s index 2a964c1c29b..658ef821f0e 100644 --- a/sim/testsuite/sim/h8300/rotr.s +++ b/sim/testsuite/sim/h8300/rotr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s index 3ae703ef800..d0ff4a3fb79 100644 --- a/sim/testsuite/sim/h8300/rotxl.s +++ b/sim/testsuite/sim/h8300/rotxl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s index 96ec8a12b6a..31a351fb23f 100644 --- a/sim/testsuite/sim/h8300/rotxr.s +++ b/sim/testsuite/sim/h8300/rotxr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s index ccea9071a8b..5d930d9da63 100644 --- a/sim/testsuite/sim/h8300/shal.s +++ b/sim/testsuite/sim/h8300/shal.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shal' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s index 9c9166be31b..6b182aa01ce 100644 --- a/sim/testsuite/sim/h8300/shar.s +++ b/sim/testsuite/sim/h8300/shar.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shar' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s index 7fbf14d056f..f21a60b81f2 100644 --- a/sim/testsuite/sim/h8300/shll.s +++ b/sim/testsuite/sim/h8300/shll.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shll' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s index 42233134b45..c9f6a08bc83 100644 --- a/sim/testsuite/sim/h8300/shlr.s +++ b/sim/testsuite/sim/h8300/shlr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shlr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s index b8aebd80dee..60bea920023 100644 --- a/sim/testsuite/sim/h8300/tas.s +++ b/sim/testsuite/sim/h8300/tas.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'tas' -# mach(): h8300h h8300s h8sx +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2