From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Sep 2020 15:42:57 +0000 (+0100)
Subject: sort out GPIO with i/o/oe in ls180
X-Git-Tag: 24jan2021_ls180~340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2f9bf79d29eac157422b53be1b2d79dccdea1de;p=soc.git

sort out GPIO with i/o/oe in ls180
---

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 68512277..4fe580ca 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -89,7 +89,7 @@ _io = [
     ("sdram", 0,
         Subsignal("a",     Pins(
             "M20 M19 L20 L19 K20 K19 K18 J20",
-            "J19 H20 N19 G20 G19")),
+            "J19 H20 N19 G20 G19 E14 E15 E16")),
         Subsignal("dq",    Pins(
             "J16 L18 M18 N18 P18 T18 T17 U20",
             "E19 D20 D19 C20 E18 F18 J18 J17")),
@@ -110,13 +110,22 @@ _io = [
 ]
 
 pins = []
-n_gpio = 12
+n_gpio = 16
 for i in range(n_gpio):
     pins.append("X%d" % i)
 pins = ' '.join(pins)
 
-# 12 GPIOs
-_io.append( ("gpio", n_gpio, Pins(pins), IOStandard("LVCMOS33")) )
+# 16 GPIOs
+#_io.append( ("gpio", 0,
+#            Subsignal("target", Pins(pins), Misc("PULLMODE=UP")),
+#            IOStandard("LVCMOS33")) )
+#_io.append( ("gpio", n_gpio, Pins(pins), IOStandard("LVCMOS33")) )
+_io.append( ("gpio", 0,
+             Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
+             Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
+             Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
+            IOStandard("LVCMOS33")) )
+#_io.append( ("gpio", n_gpio, Pins(pins), IOStandard("LVCMOS33")) )
 
 # EINT: 3 pins
 _io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 4e7fc353..8e8b7d85 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -3,7 +3,8 @@
 import os
 import argparse
 
-from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
+from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
+                   Record)
 
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
@@ -20,7 +21,6 @@ from litedram import modules as litedram_modules
 from litedram.phy.model import SDRAMPHYModel
 from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
 
-from litex.soc.cores.gpio import GPIOTristate
 from litex.soc.cores.spi import SPIMaster
 from litex.soc.cores.pwm import PWM
 from litex.soc.cores.bitbang import I2CMaster
@@ -40,6 +40,34 @@ from microwatt import Microwatt
 from litex.soc.integration.soc import SoCCSRHandler
 SoCCSRHandler.supported_address_width.append(12)
 
+# GPIO Tristate -------------------------------------------------------
+# doesn't work properly.
+#from litex.soc.cores.gpio import GPIOTristate
+from litex.soc.interconnect.csr import CSRStorage, CSRStatus
+from migen.genlib.cdc import MultiReg
+
+
+class GPIOTristateASIC(Module, AutoCSR):
+    def __init__(self, pads):
+        nbits     = len(pads.oe) # hack
+        self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
+        self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
+        self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
+
+        # # #
+
+        _pads = Record( (("i",  nbits),
+                         ("o",  nbits),
+                         ("oe", nbits)))
+        self.comb += _pads.i.eq(pads.i)
+        self.comb += pads.o.eq(_pads.o)
+        self.comb += pads.oe.eq(_pads.oe)
+
+        self.comb += _pads.oe.eq(self._oe.storage)
+        self.comb += _pads.o.eq(self._out.storage)
+        for i in range(nbits):
+            self.specials += MultiReg(_pads.i[i], self._in.status[i])
+
 
 # LibreSoCSim -----------------------------------------------------------------
 
@@ -171,13 +199,9 @@ class LibreSoCSim(SoCCore):
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
         # GPIOs (bi-directional)
-        self.submodules.gpio = GPIOTristate(platform.request("gpio"))
+        self.submodules.gpio = GPIOTristateASIC(platform.request("gpio"))
         self.add_csr("gpio")
 
-        if False:
-            self.submodules.gpio = GPIOTristate(platform.request("gpio"))
-            self.add_csr("gpio")
-
         # SPI Master
         self.submodules.spi_master = SPIMaster(
             pads         = platform.request("spi_master"),