From: lkcl Date: Thu, 17 Dec 2020 02:48:29 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1255 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a2fb1661d2bc598826106fa76e71b18f82b1f165;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index a4e91dae2..c18dfb27d 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -252,7 +252,7 @@ This is a novel concept that allows predication to be applied to a single source Those patterns (and more) may be applied to: -* mv (the usual way that V\* operations are created) +* mv (the usual way that V\* ISA operations are created) * exts\* sign-extension * rwlinm and other RS-RA shift operations (**note**: excluding those that take RA as both a src and dest. These are not @@ -265,10 +265,6 @@ This is a huge list that creates extremely powerful combinations, particularly g Additional unusual capabilities of Twin Predication include a back-to-back version of VCOMPRESS-VEXPAND which is effectively the ability to do an ordered multiple VINSERT. -## Twin Predication - -There are two different encodings: single-predication (typically arithmetic operations i.e. with more than one source register) and twin-predication (one source, one destination). They require different encodings - # Register Naming SV Registers are numbered using the notation `SV[F|C]R_` where `` is a decimal integer and `` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to ``.