From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Apr 2019 08:35:08 +0000 (+0100)
Subject: add some use of new "Elaboratable"
X-Git-Tag: div_pipeline~2144
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a30b2fe2b2f61bf95649667635ec881e3f94b23d;p=soc.git

add some use of new "Elaboratable"
---

diff --git a/TLB/src/MemorySet.py b/TLB/src/MemorySet.py
index d081dcda..ea61bdf5 100644
--- a/TLB/src/MemorySet.py
+++ b/TLB/src/MemorySet.py
@@ -1,8 +1,9 @@
-from nmigen import Cat, Memory, Module, Signal
+from nmigen import Cat, Memory, Module, Signal, Elaboratable
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 
-class MemorySet:
+
+class MemorySet(Elaboratable):
     def __init__(self, data_size, tag_size, set_count, active):
         self.active = active
         input_size = tag_size + data_size # Size of the input data
@@ -62,4 +63,4 @@ class MemorySet:
             m.d.comb += write_port.addr.eq(self.cset)
             m.d.comb += write_port.data.eq(Cat(1, self.data_i, self.tag))
 
-        return m
\ No newline at end of file
+        return m
diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index d5bad572..9afa1a28 100644
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -9,7 +9,7 @@ https://github.com/vaskevich/CacheSim/blob/master/cachesim.py
 import sys
 sys.path.append("../src/ariane")
 
-from nmigen import Array, Cat, Memory, Module, Signal, Mux
+from nmigen import Array, Cat, Memory, Module, Signal, Mux, Elaboratable
 from nmigen.compat.genlib import fsm
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
@@ -27,7 +27,8 @@ SA_NA = "00" # no action (none)
 SA_RD = "01" # read
 SA_WR = "10" # write
 
-class SetAssociativeCache():
+
+class SetAssociativeCache(Elaboratable):
     """ Set Associative Cache Memory
 
         The purpose of this module is to generate a memory cache given the
diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/plru.py
index 835c4a8e..7c4a4041 100644
--- a/TLB/src/ariane/plru.py
+++ b/TLB/src/ariane/plru.py
@@ -1,9 +1,9 @@
+from nmigen import Signal, Module, Cat, Const, Elaboratable
 from math import log2
-from nmigen import Signal, Module, Cat, Const
 
 from ptw import TLBUpdate, PTE, ASID_WIDTH
 
-class PLRU:
+class PLRU(Elaboratable):
     """ PLRU - Pseudo Least Recently Used Replacement
 
         PLRU-tree indexing:
@@ -98,4 +98,4 @@ class PLRU:
             replace.append(~Cat(*en).bool())
         m.d.comb += self.replace_en_o.eq(Cat(*replace))
 
-        return m
\ No newline at end of file
+        return m