From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Feb 2020 21:38:58 +0000 (+0000)
Subject: replace VLOG with ILANG
X-Git-Tag: partial-core-ls180-gdsii~243
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a318afffab9dc8e7ee1a3ad2542a96cf7d1063db;p=soclayout.git

replace VLOG with ILANG
---

diff --git a/mk/synthesis-yosys.mk b/mk/synthesis-yosys.mk
index 89ae3f0..653525b 100644
--- a/mk/synthesis-yosys.mk
+++ b/mk/synthesis-yosys.mk
@@ -19,12 +19,12 @@
 
  NETLISTS_NOCORONA = $(foreach netlist,$(NETLISTS)         ,$(shell echo $(netlist) | sed 's:.*_model::'))
  NETLISTS_NOMODELS = $(foreach netlist,$(NETLISTS_NOCORONA),$(shell echo $(netlist) | sed 's:.*corona::'))
- VLOG_MODULE       = $(firstword $(NETLISTS_NOMODELS))
- NETLISTS_VST      = $(shell echo $(VLOG_MODULE) | tr '[:upper:]' '[:lower:]').vst
+ ILANG_MODULE       = $(firstword $(NETLISTS_NOMODELS))
+ NETLISTS_VST      = $(shell echo $(ILANG_MODULE) | tr '[:upper:]' '[:lower:]').vst
  NETLISTS_SYNTH    = $(foreach netlist,$(NETLISTS_NOMODELS), $(shell echo $(netlist) | tr '[:upper:]' '[:lower:]'))
- CLEAN_SYNTHESIS   = $(addsuffix .vst,$(NETLISTS_SYNTH)) $(VLOG_MODULE).blif $(VLOG_MODULE).tcl
+ CLEAN_SYNTHESIS   = $(addsuffix .vst,$(NETLISTS_SYNTH)) $(ILANG_MODULE).blif $(ILANG_MODULE).tcl
 
- $(info | Verilog file & top model: "$(VLOG_MODULE)")
+ $(info | ILANG file & top model: "$(ILANG_MODULE)")
  $(info | Generated secondary VHDL structural files (vst):)
  $(foreach netlist,$(NETLISTS_SYNTH),$(info |  - "$(netlist)"))
 
@@ -53,5 +53,5 @@
 	 echo "yosys write_blif $*.blif"                    >> $*.tcl;
 	 yosys -c $*.tcl
 
-$(addsuffix .vst,$(NETLISTS_SYNTH)): $(VLOG_MODULE).blif
-	-@$(call run_if_older,$@,$(VLOG_MODULE).blif,$(call scl_cols,eval `$(CORIOLIS_TOP)/etc/coriolis2/coriolisEnv.py $(DEBUG_OPTION)`; $(BLIF2VST) $(VST_FLAGS) --cell=$(VLOG_MODULE)) )
+$(addsuffix .vst,$(NETLISTS_SYNTH)): $(ILANG_MODULE).blif
+	-@$(call run_if_older,$@,$(ILANG_MODULE).blif,$(call scl_cols,eval `$(CORIOLIS_TOP)/etc/coriolis2/coriolisEnv.py $(DEBUG_OPTION)`; $(BLIF2VST) $(VST_FLAGS) --cell=$(ILANG_MODULE)) )
diff --git a/nets.txt b/nets.txt
index c8ae834..27d0cdb 100644
--- a/nets.txt
+++ b/nets.txt
@@ -1,45 +1 @@
-part_sig_add
-mux0
-mux1
-mux2
-gtc
-reorder
-gt1
-mux0$2
-mux1$3
-mux2$4
-gtc$1
-reorder$5
-eq1
-mux0$7
-mux1$8
-mux2$9
-gtc$6
-reorder$10
-ge1
-mux0$12
-mux1$13
-mux2$14
-gtc$11
-reorder$15
-gt2
-mux0$17
-mux1$18
-mux2$19
-gtc$16
-reorder$20
-eq2
-mux0$22
-mux1$23
-mux2$24
-gtc$21
-reorder$25
-ge2
-ripple
-add1
-ripple$26
-add2
-ripple$27
-add3
-ls1
-pmux1
+part_sig_add mux0 mux1 mux2 gtc reorder gt1 mux0$2 mux1$3 mux2$4 gtc$1 reorder$5 eq1 mux0$7 mux1$8 mux2$9 gtc$6 reorder$10 ge1 mux0$12 mux1$13 mux2$14 gtc$11 reorder$15 gt2 mux0$17 mux1$18 mux2$19 gtc$16 reorder$20 eq2 mux0$22 mux1$23 mux2$24 gtc$21 reorder$25 ge2 ripple add1 ripple$26 add2 ripple$27 add3 ls1 pmux1