From: Matt Turner <mattst88@gmail.com>
Date: Tue, 14 Nov 2017 19:24:08 +0000 (-0800)
Subject: Revert "intel/fs: Use a pure vertical stride for large register strides"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a31d0382084c8aa860ffcef9b12592c5c44e192f;p=mesa.git

Revert "intel/fs: Use a pure vertical stride for large register strides"

This reverts commit e8c9e65185de3e821e1e482e77906d1d51efa3ec.

With the actual bug fixed (by commit 6ac2d1690192), this is not
necessary. I'm doubtful of its correctness in any case.
---

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 5b1121aa014..46f9a338ea2 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -90,19 +90,9 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
           *       different execution size when the number of components
           *       written to each destination GRF is not the same.
           */
-         if (reg->stride > 4) {
-            /* For registers with an exceptionally large stride, we use a
-             * width of 1 and only use the vertical stride.  This only works
-             * for sources since destinations require hstride == 1.
-             */
-            assert(reg != &inst->dst);
-            brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
-            brw_reg = stride(brw_reg, reg->stride, 1, 0);
-         } else {
-            const unsigned width = MIN2(reg_width, phys_width);
-            brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
-            brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
-         }
+         const unsigned width = MIN2(reg_width, phys_width);
+         brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
+         brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
 
          if (devinfo->gen == 7 && !devinfo->is_haswell) {
             /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):