From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 19:38:47 +0000 (-0700)
Subject: Do not check signedness of post-adder (assume taken care of by DSP)
X-Git-Tag: working-ls180~1039^2~195
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a32b14a55f888664981dc6b1184b00f34f5f4201;p=yosys.git

Do not check signedness of post-adder (assume taken care of by DSP)
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 6e82ffac3..9291c2dfb 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -52,8 +52,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 	SigSpec P = st.sigP;
 
 	if (st.postAdd) {
-		log_assert(st.postAdd->getParam("\\A_SIGNED").as_bool());
-		log_assert(st.postAdd->getParam("\\B_SIGNED").as_bool());
 		log("  adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
 
 		SigSpec &opmode = cell->connections_.at("\\OPMODE");
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index cee1906d6..fa490146c 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -173,7 +173,6 @@ match postAdd
 	if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
 
 	select postAdd->type.in($add)
-	select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
 	choice <IdString> AB {\A, \B}
 	select nusers(port(postAdd, AB)) <= 3
 	filter ffMmux || nusers(port(postAdd, AB)) == 2