From: Luke Kenneth Casson Leighton Date: Tue, 6 Oct 2020 17:05:42 +0000 (+0100) Subject: skip Decode2ToOperand from PowerDecodeSubset X-Git-Tag: 24jan2021_ls180~206 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a32e62f251e9217d85072a8b24bd580950e193a5;p=soc.git skip Decode2ToOperand from PowerDecodeSubset --- diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index 9442af68..d7185326 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -83,9 +83,9 @@ class Decode2ToOperand(IssuerDecode2ToOperand): class Decode2ToExecute1Type(RecordObject): - def __init__(self, name=None, asmcode=True, opkls=None): + def __init__(self, name=None, asmcode=True, opkls=None, do=None): - if opkls is None: + if do is None and opkls is None: opkls = Decode2ToOperand RecordObject.__init__(self, name=name) @@ -115,6 +115,9 @@ class Decode2ToExecute1Type(RecordObject): self.write_cr = Data(3, name="cr_out") # decode operand data - print ("decode2execute init", name, opkls) + print ("decode2execute init", name, opkls, do) #assert name is not None, str(opkls) - self.do = opkls(name) + if do is not None: + self.do = do + else: + self.do = opkls(name) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index ced6e9f5..5e89916a 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -23,7 +23,8 @@ from soc.decoder.power_enums import (MicrOp, CryIn, Function, CRInSel, CROutSel, LdstLen, In1Sel, In2Sel, In3Sel, OutSel, SPR, RC, LDSTMode) -from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data +from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data, + Decode2ToOperand) from soc.consts import MSR from soc.regfile.regfiles import FastRegs @@ -628,8 +629,12 @@ class PowerDecodeSubset(Elaboratable): self.final = final self.opkls = opkls self.fn_name = fn_name - self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls) - col_subset = self.get_col_subset(self.e.do) + if opkls is None: + opkls = Decode2ToOperand + self.do = opkls(fn_name) + if not self.final: + self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do) + col_subset = self.get_col_subset(self.do) # create decoder if one not already given if dec is None: @@ -658,14 +663,14 @@ class PowerDecodeSubset(Elaboratable): def needs_field(self, field, op_field): if self.final: - do = self.e.do + do = self.do else: do = self.e_tmp.do return hasattr(do, field) and self.op_get(op_field) is not None def do_copy(self, field, val, final=False): if final or self.final: - do = self.e.do + do = self.do else: do = self.e_tmp.do if hasattr(do, field) and val is not None: @@ -679,20 +684,17 @@ class PowerDecodeSubset(Elaboratable): m = Module() comb = m.d.comb state = self.state - e_out, op, do_out = self.e, self.dec.op, self.e.do + op, do = self.dec.op, self.do msr, cia = state.msr, state.pc # fill in for a normal instruction (not an exception) # copy over if non-exception, non-privileged etc. is detected - if self.final: - e = self.e - else: + if not self.final: if self.fn_name is None: name = "tmp" else: name = self.fn_name + "tmp" - self.e_tmp = e = Decode2ToExecute1Type(name=name, opkls=self.opkls) - do = e.do + self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls) # set up submodule decoders m.submodules.dec = self.dec @@ -916,7 +918,7 @@ class PowerDecode2(PowerDecodeSubset): with m.If(exc.segment_fault): self.trap(m, TT.PRIV, 0x480) with m.Else(): - #spass exception info to trap to create SRR1 + # pass exception info to trap to create SRR1 self.trap(m, TT.MEMEXC, 0x400, exc) with m.Else(): with m.If(exc.segment_fault): diff --git a/src/soc/fu/base_input_record.py b/src/soc/fu/base_input_record.py index e39daef8..524ad073 100644 --- a/src/soc/fu/base_input_record.py +++ b/src/soc/fu/base_input_record.py @@ -35,7 +35,7 @@ class CompOpSubsetBase(Record): def eq_from_execute1(self, other): """ use this to copy in from Decode2Execute1Type """ - return self.eq_from(other.do) + return self.eq_from(other) def ports(self): res = [] diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 03e76435..b1511f88 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -75,7 +75,7 @@ def set_cu_inputs(cu, inp): def set_operand(cu, dec2, sim): - yield from cu.oper_i.eq_from_execute1(dec2.e) + yield from cu.oper_i.eq_from_execute1(dec2.do) yield cu.issue_i.eq(1) yield yield cu.issue_i.eq(0) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 1cc4c423..ed9d72d2 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -200,7 +200,7 @@ class TestRunner(unittest.TestCase): pspec = TrapPipeSpec(id_wid=2) m.submodules.alu = alu = TrapBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) + comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.p.valid_i.eq(1) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index d9dcfeb4..7479be12 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -105,7 +105,7 @@ class NonProductionCore(Elaboratable): # create per-FU instruction decoders (subsetted) self.decoders = {} - self.ees = {} + self.des = {} for funame, fu in self.fus.fus.items(): f_name = fu.fnunit.name @@ -117,7 +117,7 @@ class NonProductionCore(Elaboratable): self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name, final=True, state=self.state) - self.ees[funame] = self.decoders[funame].e + self.des[funame] = self.decoders[funame].do def elaborate(self, platform): m = Module() @@ -139,7 +139,7 @@ class NonProductionCore(Elaboratable): comb += v.dec.bigendian.eq(self.bigendian_i) # ssh, cheat: trap uses the main decoder because of the rewriting - self.ees[self.trapunit] = self.e + self.des[self.trapunit] = self.e.do # connect up Function Units, then read/write ports fu_bitdict = self.connect_instruction(m) @@ -200,14 +200,14 @@ class NonProductionCore(Elaboratable): with m.Default(): # connect up instructions. only one enabled at a time for funame, fu in fus.items(): - e = self.ees[funame] + do = self.des[funame] enable = fu_bitdict[funame] # run this FunctionUnit if enabled # route op, issue, busy, read flags and mask to FU with m.If(enable): # operand comes from the *local* decoder - comb += fu.oper_i.eq_from(e.do) + comb += fu.oper_i.eq_from(do) #comb += fu.oper_i.eq_from_execute1(e) comb += fu.issue_i.eq(self.issue_i) comb += self.busy_o.eq(fu.busy_o)