From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 21 Apr 2019 21:24:50 +0000 (-0700)
Subject: Merge branch 'master' into map_cells_before_map_luts
X-Git-Tag: yosys-0.9~183^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3371e118b05eb9bd5dddb1c20758674ae50a803;p=yosys.git

Merge branch 'master' into map_cells_before_map_luts
---

a3371e118b05eb9bd5dddb1c20758674ae50a803
diff --cc techlibs/xilinx/synth_xilinx.cc
index b82ab9337,397c83ac6..da6c0a4b2
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -110,20 -110,20 +110,20 @@@ struct SynthXilinxPass : public Pas
  		log("        dffsr2dff\n");
  		log("        dff2dffe\n");
  		log("        opt -full\n");
- 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+ 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
  		log("        opt -fast\n");
  		log("\n");
 +		log("    map_cells:\n");
 +		log("        techmap -map +/xilinx/cells_map.v\n");
- 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
- 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 +		log("        clean\n");
 +		log("\n");
  		log("    map_luts:\n");
- 		log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
- 		log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
+ 		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
+ 		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
  		log("        clean\n");
- 		log("        techmap -map +/xilinx/lut_map.v\n");
+ 		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 -		log("\n");
 -		log("    map_cells:\n");
 -		log("        techmap -map +/xilinx/cells_map.v\n");
+ 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
+ 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 -		log("        clean\n");
  		log("\n");
  		log("    check:\n");
  		log("        hierarchy -check\n");
@@@ -266,19 -266,20 +266,20 @@@
  			Pass::call(design, "opt -fast");
  		}
  
 +		if (check_label(active, run_from, run_to, "map_cells"))
 +		{
 +			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
- 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
- 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 +			Pass::call(design, "clean");
 +		}
 +
  		if (check_label(active, run_from, run_to, "map_luts"))
  		{
+ 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
  			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
  			Pass::call(design, "clean");
- 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
+ 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 -		}
 -
 -		if (check_label(active, run_from, run_to, "map_cells"))
 -		{
 -			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+ 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+ 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 -			Pass::call(design, "clean");
  		}
  
  		if (check_label(active, run_from, run_to, "check"))