From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 5 Jun 2017 12:33:46 +0000 (+0200)
Subject: gen/fhdl/verilog: list available clock domains on keyerror
X-Git-Tag: 24jan2021_ls180~1849
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a36986a501978084491148a8f2b860b2e374d452;p=litex.git

gen/fhdl/verilog: list available clock domains on keyerror
---

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 1fb6024b..d5aef8d6 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -339,6 +339,9 @@ def convert(f, ios=None, name="top",
                 f.clock_domains.append(cd)
                 ios |= {cd.clk, cd.rst}
             else:
+                print("available clock domains:")
+                for f in f.clock_domains:
+                    print(f.name)
                 raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 
     f = lower_complex_slices(f)