From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Dec 2021 15:45:33 +0000 (+0000)
Subject: add I-Cache to FSM local variables
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a374f26022748d4fe03e03ca3b0e8d85ffa82d66;p=soc.git

add I-Cache to FSM local variables
---

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index a73a89bc..a40c2727 100644
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -21,3 +21,6 @@ class ConfigFetchUnit:
         fukls = fudict[pspec.imem_ifacetype]
         self.fu = fukls(pspec)
 
+    def wb_bus(self):
+        return self.fu.ibus
+
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index ae71f97b..7e8a699f 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -65,6 +65,7 @@ class FSMMMUStage(ControlBase):
         # incoming PortInterface
         self.ldst = ldst
         self.dcache = self.ldst.dcache
+        self.icache = self.ldst.icache
         self.pi = self.ldst.pi
 
     def elaborate(self, platform):