From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Jul 2019 21:52:14 +0000 (-0700)
Subject: Fix muxAB logic
X-Git-Tag: working-ls180~1039^2~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a37574ccbfe047c09a60bb6ee68b7b5e2ef61337;p=yosys.git

Fix muxAB logic
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 24247d3cf..4b566f0a6 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -187,10 +187,9 @@ code clock clock_pol sigO sigCD sigCD_signed
 
 		// Loading value into output register is not
 		//   supported unless using accumulator
-		if (muxAB && sigCD != sigO) {
-			if (muxAB != addAB)
+		if (muxAB) {
+			if (sigCD != sigO)
 				reject;
-
 			if (muxA)
 				sigCD = port(muxAB, \B);
 			else if (muxB)