From: lkcl Date: Thu, 8 Sep 2022 14:36:59 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~624 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a376cdeb44414476d881994c172e46031030ac39;p=libreriscv.git --- diff --git a/openpower/sv/rfc/001.mdwn b/openpower/sv/rfc/001.mdwn index dfb52509d..7e841b516 100644 --- a/openpower/sv/rfc/001.mdwn +++ b/openpower/sv/rfc/001.mdwn @@ -63,7 +63,10 @@ they are all required * No new Interrupt types are required. * Register numbers are extended to 128 (including CR Fields). A future version may extend to 256 or beyond [^extend] +* 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO) +* Another 24-bit (a second 2-bit XO) is needed for a planned future encoding, currently + named "SVP64-Single" [^likeext001] +* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved** - -[^extend]: Prefix opcode space **must** be reserved in advance to to so, in order to avoid the catastrophic mistake made by RISC-V RVV and ARM SVE/2 - +[^extend]: Prefix opcode space **must** be reserved in advance to to so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2 +[^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations.