From: Jason Ekstrand Date: Sat, 6 Feb 2016 02:39:13 +0000 (-0800) Subject: i965/fs: Add an enum for keeping track of texture instruciton sources X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a37b8110c13bf9e38220d6eb9e531b2acffcb4ed;p=mesa.git i965/fs: Add an enum for keeping track of texture instruciton sources These logical texture instructions can have a *lot* of sources. It's much safer if we have symbolic names for them. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 01e0c99e440..938770fe6b9 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -968,19 +968,8 @@ enum opcode { * * LOGICAL opcodes are eventually translated to the matching non-LOGICAL * opcode but instead of taking a single payload blob they expect their - * arguments separately as individual sources: - * - * Source 0: [optional] Texture coordinates. - * Source 1: [optional] Shadow comparitor. - * Source 2: [optional] dPdx if the operation takes explicit derivatives, - * otherwise LOD value. - * Source 3: [optional] dPdy if the operation takes explicit derivatives. - * Source 4: [optional] Sample index. - * Source 5: [optional] MCS data. - * Source 6: [required] Texture sampler. - * Source 7: [optional] Texel offset. - * Source 8: [required] Number of coordinate components (as UD immediate). - * Source 9: [required] Number derivative components (as UD immediate). + * arguments separately as individual sources. The position/ordering of the + * arguments are defined by the enum tex_logical_srcs. */ SHADER_OPCODE_TEX, SHADER_OPCODE_TEX_LOGICAL, @@ -1404,6 +1393,31 @@ enum fb_write_logical_srcs { FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */ }; +enum tex_logical_srcs { + /** Texture coordinates */ + TEX_LOGICAL_SRC_COORDINATE, + /** Shadow comparitor */ + TEX_LOGICAL_SRC_SHADOW_C, + /** dPdx if the operation takes explicit derivatives, otherwise LOD value */ + TEX_LOGICAL_SRC_LOD, + /** dPdy if the operation takes explicit derivatives */ + TEX_LOGICAL_SRC_LOD2, + /** Sample index */ + TEX_LOGICAL_SRC_SAMPLE_INDEX, + /** MCS data */ + TEX_LOGICAL_SRC_MCS, + /** REQUIRED: Texture sampler */ + TEX_LOGICAL_SRC_SAMPLER, + /** Texel offset for gathers */ + TEX_LOGICAL_SRC_OFFSET_VALUE, + /** REQUIRED: Number of coordinate components (as UD immediate) */ + TEX_LOGICAL_SRC_COORD_COMPONENTS, + /** REQUIRED: Number of derivative components (as UD immediate) */ + TEX_LOGICAL_SRC_GRAD_COMPONENTS, + + TEX_LOGICAL_NUM_SRCS, +}; + #ifdef __cplusplus /** * Allow brw_urb_write_flags enums to be ORed together. diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 41a3f81b9d8..18a56f6d3fa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -739,18 +739,20 @@ fs_inst::components_read(unsigned i) const case SHADER_OPCODE_LOD_LOGICAL: case SHADER_OPCODE_TG4_LOGICAL: case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - assert(src[8].file == IMM && src[9].file == IMM); + assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM && + src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM); /* Texture coordinates. */ - if (i == 0) - return src[8].ud; + if (i == TEX_LOGICAL_SRC_COORDINATE) + return src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud; /* Texture derivatives. */ - else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL) - return src[9].ud; + else if ((i == TEX_LOGICAL_SRC_LOD || i == TEX_LOGICAL_SRC_LOD2) && + opcode == SHADER_OPCODE_TXD_LOGICAL) + return src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud; /* Texture offset. */ - else if (i == 7) + else if (i == TEX_LOGICAL_SRC_OFFSET_VALUE) return 2; /* MCS */ - else if (i == 5 && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL) + else if (i == TEX_LOGICAL_SRC_MCS && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL) return 2; else return 1; @@ -4080,17 +4082,18 @@ static void lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) { const brw_device_info *devinfo = bld.shader->devinfo; - const fs_reg &coordinate = inst->src[0]; - const fs_reg &shadow_c = inst->src[1]; - const fs_reg &lod = inst->src[2]; - const fs_reg &lod2 = inst->src[3]; - const fs_reg &sample_index = inst->src[4]; - const fs_reg &mcs = inst->src[5]; - const fs_reg &sampler = inst->src[6]; - const fs_reg &offset_value = inst->src[7]; - assert(inst->src[8].file == IMM && inst->src[9].file == IMM); - const unsigned coord_components = inst->src[8].ud; - const unsigned grad_components = inst->src[9].ud; + const fs_reg &coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE]; + const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C]; + const fs_reg &lod = inst->src[TEX_LOGICAL_SRC_LOD]; + const fs_reg &lod2 = inst->src[TEX_LOGICAL_SRC_LOD2]; + const fs_reg &sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX]; + const fs_reg &mcs = inst->src[TEX_LOGICAL_SRC_MCS]; + const fs_reg &sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER]; + const fs_reg &offset_value = inst->src[TEX_LOGICAL_SRC_OFFSET_VALUE]; + assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM); + const unsigned coord_components = inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud; + assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM); + const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud; if (devinfo->gen >= 7) { lower_sampler_logical_send_gen7(bld, inst, op, coordinate, @@ -4384,7 +4387,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, case SHADER_OPCODE_TG4_OFFSET_LOGICAL: { /* gather4_po_c is unsupported in SIMD16 mode. */ - const fs_reg &shadow_c = inst->src[1]; + const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C]; return (shadow_c.file != BAD_FILE ? 8 : inst->exec_size); } case SHADER_OPCODE_TXL_LOGICAL: @@ -4393,7 +4396,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16 * mode because the message exceeds the maximum length of 11. */ - const fs_reg &shadow_c = inst->src[1]; + const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C]; if (devinfo->gen == 4 && shadow_c.file == BAD_FILE) return 16; else if (devinfo->gen < 7 && shadow_c.file != BAD_FILE) @@ -4416,7 +4419,8 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, * circumstances it can end up with a message that is too long in SIMD16 * mode. */ - const unsigned coord_components = inst->src[8].ud; + const unsigned coord_components = + inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud; /* First three arguments are the sample index and the two arguments for * the MCS data. */ diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index a74ed7247db..ad68b2d3380 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -82,10 +82,13 @@ fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components, const fs_reg &sampler) { const fs_reg dest = vgrf(glsl_type::uvec4_type); - const fs_reg srcs[] = { - coordinate, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(), - sampler, fs_reg(), brw_imm_ud(components), brw_imm_d(0) - }; + + fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate; + srcs[TEX_LOGICAL_SRC_SAMPLER] = sampler; + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0); + fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, ARRAY_SIZE(srcs)); @@ -145,13 +148,20 @@ fs_visitor::emit_texture(ir_texture_opcode op, * samples, so don't worry about them. */ fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1)); - const fs_reg srcs[] = { - coordinate, shadow_c, lod, lod2, - sample_index, mcs, sampler_reg, offset_value, - brw_imm_d(coord_components), brw_imm_d(grad_components) - }; - enum opcode opcode; + fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate; + srcs[TEX_LOGICAL_SRC_SHADOW_C] = shadow_c; + srcs[TEX_LOGICAL_SRC_LOD] = lod; + srcs[TEX_LOGICAL_SRC_LOD2] = lod2; + srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = sample_index; + srcs[TEX_LOGICAL_SRC_MCS] = mcs; + srcs[TEX_LOGICAL_SRC_SAMPLER] = sampler_reg; + srcs[TEX_LOGICAL_SRC_OFFSET_VALUE] = offset_value; + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(coord_components); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(grad_components); + + enum opcode opcode; switch (op) { case ir_tex: opcode = SHADER_OPCODE_TEX_LOGICAL;