From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Thu, 1 Aug 2013 04:33:25 +0000 (-0700)
Subject: Fix eret (again)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a39658bf83c03c734fef210131d649540940258a;p=riscv-isa-sim.git

Fix eret (again)

* Set SR_S if SR_PS is set, not the other way around
  (that is, set SR_S if SR_PS is not set).
---

diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h
index deed103..9ea8baf 100644
--- a/riscv/insns/eret.h
+++ b/riscv/insns/eret.h
@@ -1,5 +1,5 @@
 require_supervisor;
 set_pcr(PCR_SR, ((sr & ~(SR_S | SR_EI)) |
-                ((sr & SR_PS) ? 0 : SR_S)) |
+                ((sr & SR_PS) ? SR_S : 0)) |
                 ((sr & SR_PEI) ? SR_EI : 0));
 set_pc(epc);