From: Luke Kenneth Casson Leighton Date: Thu, 18 Apr 2019 19:55:18 +0000 (+0100) Subject: random experiments with ptw.py X-Git-Tag: div_pipeline~2222 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3b763924d2682dc0aefc85d203ccf581901ced1;p=soc.git random experiments with ptw.py --- diff --git a/TLB/src/ariane/test_ptw.py b/TLB/src/ariane/test_ptw.py index 7132eb4f..35581bdb 100644 --- a/TLB/src/ariane/test_ptw.py +++ b/TLB/src/ariane/test_ptw.py @@ -1,23 +1,49 @@ from nmigen.compat.sim import run_simulation -from ptw import PTW +from ptw import PTW, PTE def testbench(dut): + + addr = 0x8000000 + + #pte = PTE() + #yield pte.v.eq(1) + #yield pte.r.eq(1) + yield dut.req_port_i.data_gnt.eq(1) yield dut.req_port_i.data_rvalid.eq(1) - yield dut.req_port_i.data_rdata.eq(0x0001) + yield dut.req_port_i.data_rdata.eq(0xc2<<56)#pte.flatten()) - yield dut.enable_translation_i.eq(1) + yield dut.en_ld_st_translation_i.eq(1) yield dut.asid_i.eq(1) - yield dut.itlb_access_i.eq(1) - yield dut.itlb_hit_i.eq(0) - yield dut.itlb_vaddr_i.eq(0x0001) + yield dut.dtlb_access_i.eq(1) + yield dut.dtlb_hit_i.eq(0) + yield dut.dtlb_vaddr_i.eq(0x400000000) + + yield + yield + yield + + yield dut.dtlb_access_i.eq(1) + yield dut.dtlb_hit_i.eq(0) + yield dut.dtlb_vaddr_i.eq(0x200000) yield yield yield + + yield dut.req_port_i.data_gnt.eq(0) + yield dut.dtlb_access_i.eq(1) + yield dut.dtlb_hit_i.eq(0) + yield dut.dtlb_vaddr_i.eq(0x400000011) + + yield + yield dut.req_port_i.data_gnt.eq(1) + yield + yield + yield diff --git a/TLB/src/ariane/test_tlb.py b/TLB/src/ariane/test_tlb.py index 2ef887c1..bebca7f0 100644 --- a/TLB/src/ariane/test_tlb.py +++ b/TLB/src/ariane/test_tlb.py @@ -10,11 +10,9 @@ def set_vaddr(addr): def testbench(dut): yield dut.lu_access_i.eq(1) yield dut.lu_asid_i.eq(1) - yield dut.lu_vaddr_i.eq(0x80000) yield dut.update_i.valid.eq(1) yield dut.update_i.is_1G.eq(0) yield dut.update_i.is_2M.eq(0) - yield dut.update_i.vpn.eq(0x80000) yield dut.update_i.asid.eq(1) yield dut.update_i.content.ppn.eq(0) yield dut.update_i.content.rsw.eq(0)