From: Carl Love <cel@us.ibm.com>
Date: Fri, 20 Apr 2018 15:18:24 +0000 (+0000)
Subject: re PR target/83402 (PPC64 implementation of ./rs6000/emmintrin.h gives out of range... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3b82e156de228bbd33c87999f1fbdd519140734;p=gcc.git

re PR target/83402 (PPC64 implementation of ./rs6000/emmintrin.h gives out of range for _mm_slli_epi32)


gcc/ChangeLog:

2018-04-20  Carl Love  <cel@us.ibm.com>

        PR target/83402
        * config/rs6000/rs6000-c.c (rs6000_gimple_fold_builtin): Add
        size check for arg0.

From-SVN: r259524
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7152a1942a7..1702d952023 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-04-20  Carl Love  <cel@us.ibm.com>
+
+        PR target/83402
+        * config/rs6000/rs6000-c.c (rs6000_gimple_fold_builtin): Add
+        size check for arg0.
+
 2018-04-20  Nathan Sidwell  <nathan@codesourcery.com>
 	    Tom de Vries  <tom@codesourcery.com>
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fd11407367e..7ba908e520e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16594,10 +16594,23 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     case ALTIVEC_BUILTIN_VSPLTISH:
     case ALTIVEC_BUILTIN_VSPLTISW:
       {
+	 int size;
+
+         if (fn_code == ALTIVEC_BUILTIN_VSPLTISB)
+           size = 8;
+         else if (fn_code == ALTIVEC_BUILTIN_VSPLTISH)
+           size = 16;
+         else
+           size = 32;
+
 	 arg0 = gimple_call_arg (stmt, 0);
 	 lhs = gimple_call_lhs (stmt);
-	 /* Only fold the vec_splat_*() if arg0 is constant.  */
-	 if (TREE_CODE (arg0) != INTEGER_CST)
+
+	 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
+	    5-bit signed constant in range -16 to +15.  */
+	 if (TREE_CODE (arg0) != INTEGER_CST
+	     || !IN_RANGE (sext_hwi(TREE_INT_CST_LOW (arg0), size),
+			   -16, 15))
 	   return false;
 	 gimple_seq stmts = NULL;
 	 location_t loc = gimple_location (stmt);